DWC_pcie_dbi_cpcie_dsp_4x8.csr/project/jenkins/workspace/Esperanto_DV/soc_hal/esperanto-soc/dv/common/scripts/semifore_css/etsoc_esr.cssPE0_DWC_pcie_ctlcomponentPE0_DWC_pcie_ctlPE0_DWC_pcie_ctlDWC_pcie_dbi_cpcie_dsp_4x8.csr109231NAPE0_DWC_pcie_ctladdressmapPE0_DWC_pcie_ctl.AXI_SlaveaddressmapPE0_DWC_pcie_ctl.DBI_SlaveaddressmapPE0_DWC_pcie_ctl.AXI_SlaveAXI_SlaveDWC_pcie_dbi_cpcie_dsp_4x8.csr109229R/WPE0_DWC_pcie_ctl_AXI_SlaveDWC PCIE-RC Memory MapgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDRgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGICmemoryPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP_DBI2groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP0x00x381123AXI_SlavePE0_DWC_pcie_ctl.AXI_Slave0x00x3FAXI_Slave.PF0_TYPE1_HDRPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR0x00x0AXI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REG0x40x4AXI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REG0x80x8AXI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REG0xC0xCAXI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG0x100x10AXI_Slave.PF0_TYPE1_HDR.BAR0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BAR0_REG0x140x14AXI_Slave.PF0_TYPE1_HDR.BAR1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BAR1_REG0x180x18AXI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG0x1C0x1CAXI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REG0x200x20AXI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REG0x240x24AXI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REG0x280x28AXI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REG0x2C0x2CAXI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REG0x300x30AXI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REG0x340x34AXI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REG0x380x38AXI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REG0x3C0x3CAXI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REG0x400x47AXI_Slave.PF0_PM_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP0x400x40AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REG0x440x44AXI_Slave.PF0_PM_CAP.CON_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CON_STATUS_REG0x480x4F0x500x67AXI_Slave.PF0_MSI_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP0x500x50AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REG0x540x54AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REG0x580x58AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REG0x5C0x5CAXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REG0x600x60AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REG0x640x64AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REG0x680x6F0x700xABAXI_Slave.PF0_PCIE_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP0x700x70AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG0x740x74AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REG0x780x78AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUS0x7C0x7CAXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REG0x800x80AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REG0x840x84AXI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REG0x880x88AXI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUSPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUS0x8C0x8CAXI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REG0x900x90AXI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REG0x940x94AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REG0x980x98AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REG0x9C0x9CAXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REG0xA00xA0AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REG0xA40xAB0xAC0xAF0xB00xBCAXI_Slave.PF0_MSIX_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP0xB00xB0AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REG0xB40xB4AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REG0xB80xB8AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REG0xBC0xBC0xBD0xFF0x1000x147AXI_Slave.PF0_AER_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP0x1000x100AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFF0x1040x104AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFF0x1080x108AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFF0x10C0x10CAXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFF0x1100x110AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFF0x1140x114AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFF0x1180x118AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFF0x11C0x11CAXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFF0x1200x120AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFF0x1240x124AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFF0x1280x128AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFF0x12C0x12CAXI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFF0x1300x130AXI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFF0x1340x134AXI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFF0x1380x138AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFF0x13C0x13CAXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFF0x1400x140AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFF0x1440x144AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFF0x1480x197AXI_Slave.PF0_VC_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP0x1480x148AXI_Slave.PF0_VC_CAP.VC_BASEPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_BASE0x14C0x14CAXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_10x1500x150AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_20x1540x154AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REG0x1580x158AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC00x15C0x15CAXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC00x1600x160AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC00x1640x164AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC10x1680x168AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC10x16C0x16CAXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC10x1700x170AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC20x1740x174AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC20x1780x178AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC20x17C0x17CAXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC30x1800x180AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC30x1840x184AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3PE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC30x1880x1970x1980x1B7AXI_Slave.PF0_SPCIE_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP0x1980x198AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REG0x19C0x19CAXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REG0x1A00x1A0AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REG0x1A40x1A4AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REG0x1A80x1A8AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REG0x1AC0x1ACAXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REG0x1B00x1B0AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REG0x1B40x1B70x1B80x1DFAXI_Slave.PF0_PL16G_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP0x1B80x1B8AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REG0x1BC0x1BCAXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REG0x1C00x1C0AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REG0x1C40x1C4AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REG0x1C80x1C8AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REG0x1CC0x1CCAXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REG0x1D00x1D0AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REG0x1D40x1D70x1D80x1D8AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REG0x1DC0x1DCAXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REG0x1E00x207AXI_Slave.PF0_MARGIN_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP0x1E00x1E0AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REG0x1E40x1E4AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REG0x1E80x1E8AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REG0x1EC0x1ECAXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REG0x1F00x1F0AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REG0x1F40x1F4AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REG0x1F80x1F8AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REG0x1FC0x1FCAXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REG0x2000x200AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REG0x2040x204AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REG0x2080x293AXI_Slave.PF0_TPH_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP0x2080x208AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REG0x20C0x20CAXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REG0x2100x210AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REG0x2140x214AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_00x2180x2930x2940x29B0x29C0x2ABAXI_Slave.PF0_L1SUB_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP0x29C0x29CAXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REG0x2A00x2A0AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REG0x2A40x2A4AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REG0x2A80x2A8AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REG0x2AC0x2BBAXI_Slave.PF0_FRSQ_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP0x2AC0x2ACAXI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFF0x2B00x2B0AXI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFF0x2B40x2B4AXI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFF0x2B80x2B8AXI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFF0x2BC0x2C30x2C40x3C3AXI_Slave.PF0_RAS_DES_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP0x2C40x2C4AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REG0x2C80x2C8AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REG0x2CC0x2CCAXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REG0x2D00x2D0AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REG0x2D40x2D4AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REG0x2D80x2D8AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REG0x2DC0x2DCAXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REG0x2E00x2F30x2F40x2F4AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REG0x2F80x2F8AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REG0x2FC0x2FCAXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REG0x3000x300AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REG0x3040x304AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REG0x3080x308AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REG0x30C0x30CAXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REG0x3100x310AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REG0x3140x314AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REG0x3180x318AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REG0x31C0x31CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REG0x3200x320AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REG0x3240x324AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REG0x3280x328AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REG0x32C0x32CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REG0x3300x330AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REG0x3340x334AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REG0x3380x338AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REG0x33C0x33CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REG0x3400x340AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REG0x3440x344AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REG0x3480x348AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REG0x34C0x34CAXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REG0x3500x350AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REG0x3540x3630x3640x364AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REG0x3680x368AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REG0x36C0x3730x3740x374AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REG0x3780x378AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REG0x37C0x37CAXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REG0x3800x380AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REG0x3840x384AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REG0x3880x388AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REG0x38C0x3930x3940x394AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REG0x3980x398AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REG0x39C0x39CAXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REG0x3A00x3A30x3A40x3A4AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REG0x3A80x3A8AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REG0x3AC0x3ACAXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REG0x3B00x3C30x3C40x3FBAXI_Slave.PF0_VSECRAS_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP0x3C40x3C4AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFF0x3C80x3C8AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFF0x3CC0x3CCAXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFF0x3D00x3D0AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFF0x3D40x3D4AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFF0x3D80x3D8AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFF0x3DC0x3DCAXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFF0x3E00x3E0AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFF0x3E40x3E4AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFF0x3E80x3E8AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFF0x3EC0x3ECAXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFF0x3F00x3F0AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFF0x3F40x3F4AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFF0x3F80x3F8AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFF0x3FC0x407AXI_Slave.PF0_DLINK_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP0x3FC0x3FCAXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFF0x4000x400AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFF0x4040x404AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFF0x4080x6FF0x7000xCFFAXI_Slave.PF0_PORT_LOGICPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC0x7000x700AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFF0x7040x704AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFF0x7080x708AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFF0x70C0x70CAXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFF0x7100x710AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFF0x7140x714AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFF0x7180x718AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFF0x71C0x71CAXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFF0x7200x720AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFF0x7240x724AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF0x7280x728AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFF0x72C0x72CAXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFF0x7300x730AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFF0x7340x734AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFF0x7380x738AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFF0x73C0x73CAXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFF0x7400x740AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFF0x7440x744AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFF0x7480x748AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFF0x74C0x74CAXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFF0x7500x750AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFF0x7540x754AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFF0x7580x758AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFF0x75C0x75CAXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFF0x7600x760AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFF0x7640x764AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFF0x7680x768AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFF0x76C0x76CAXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFF0x7700x770AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFF0x7740x774AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFF0x7780x80B0x80C0x80CAXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFF0x8100x810AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFF0x8140x814AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFF0x8180x81B0x81C0x81CAXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFF0x8200x820AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFF0x8240x824AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFF0x8280x828AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFF0x82C0x82CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFF0x8300x830AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFF0x8340x834AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFF0x8380x838AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFF0x83C0x83CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFF0x8400x840AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFF0x8440x844AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFF0x8480x848AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFF0x84C0x84CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFF0x8500x850AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFF0x8540x854AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFF0x8580x858AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFF0x85C0x85CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFF0x8600x860AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFF0x8640x864AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFF0x8680x868AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFF0x86C0x86CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFF0x8700x870AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFF0x8740x874AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFF0x8780x878AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFF0x87C0x87CAXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFF0x8800x880AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFF0x8840x884AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFF0x8880x888AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFF0x88C0x88CAXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFF0x8900x890AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFF0x8940x8A70x8A80x8A8AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFF0x8AC0x8ACAXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFF0x8B00x8B30x8B40x8B4AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFF0x8B80x8B8AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFF0x8BC0x8BCAXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFF0x8C00x8C0AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFF0x8C40x8C4AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFF0x8C80x8C8AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFF0x8CC0x8CCAXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFF0x8D00x8D0AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFF0x8D40x8D4AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFF0x8D80x8D8AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFF0x8DC0x8DF0x8E00x8E0AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFF0x8E40x8E4AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFF0x8E80x8E8AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFF0x8EC0x8EF0x8F00x8F0AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFF0x8F40x8F4AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFF0x8F80x8F8AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFF0x8FC0x8FCAXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFF0x9000x93F0x9400x940AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFF0x9440x944AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFF0x9480x948AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFF0x94C0x94CAXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFF0x9500xB2F0xB300xB30AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFF0xB340xB3F0xB400xB40AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFF0xB440xB44AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFF0xB480xB48AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFF0xB4C0xB7F0xB800xB80AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFF0xB840xB84AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFF0xB880xB8F0xB900xB90AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFF0xB940xCFF0xD000x10006F0x1000700x1000ABAXI_Slave.PF0_PCIE_CAP_DBI2PE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP_DBI20x1000AC0x1000AF0x1000B00x1000BCAXI_Slave.PF0_MSIX_CAP_DBI2PE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI20x1000B00x1000B0AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG0x1000B40x1000B4AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REG0x1000B80x1000B8AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REG0x1000BC0x1000BC0x1000BD0x1002070x1002080x100293AXI_Slave.PF0_TPH_CAP_DBI2PE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI20x1002080x10020B0x10020C0x10020CAXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REG0x1002100x1002930x1002940x2FFFFF0x3000000x31FF23AXI_Slave.PF0_ATU_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP0x3000000x300000AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_00x3000040x300004AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_00x3000080x300008AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_00x30000C0x30000CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_00x3000100x300010AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_00x3000140x300014AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_00x3000180x300018AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_00x30001C0x30001F0x3000200x300020AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_00x3000240x3000FF0x3001000x300100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_00x3001040x300104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_00x3001080x300108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_00x30010C0x30010CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_00x3001100x300110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_00x3001140x300114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_00x3001180x300118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_00x30011C0x30011F0x3001200x300120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_00x3001240x3001FF0x3002000x300200AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10x3002040x300204AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10x3002080x300208AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10x30020C0x30020CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10x3002100x300210AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10x3002140x300214AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10x3002180x300218AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10x30021C0x30021F0x3002200x300220AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10x3002240x3002FF0x3003000x300300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10x3003040x300304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10x3003080x300308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10x30030C0x30030CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10x3003100x300310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10x3003140x300314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10x3003180x300318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10x30031C0x30031F0x3003200x300320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10x3003240x3003FF0x3004000x300400AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_20x3004040x300404AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_20x3004080x300408AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_20x30040C0x30040CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_20x3004100x300410AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_20x3004140x300414AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_20x3004180x300418AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_20x30041C0x30041F0x3004200x300420AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_20x3004240x3004FF0x3005000x300500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20x3005040x300504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20x3005080x300508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20x30050C0x30050CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20x3005100x300510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20x3005140x300514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20x3005180x300518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20x30051C0x30051F0x3005200x300520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20x3005240x3005FF0x3006000x300600AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_30x3006040x300604AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_30x3006080x300608AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_30x30060C0x30060CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_30x3006100x300610AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_30x3006140x300614AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_30x3006180x300618AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_30x30061C0x30061F0x3006200x300620AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_30x3006240x3006FF0x3007000x300700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30x3007040x300704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30x3007080x300708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30x30070C0x30070CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30x3007100x300710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30x3007140x300714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30x3007180x300718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30x30071C0x30071F0x3007200x300720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30x3007240x3007FF0x3008000x300800AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_40x3008040x300804AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_40x3008080x300808AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_40x30080C0x30080CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_40x3008100x300810AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_40x3008140x300814AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_40x3008180x300818AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_40x30081C0x30081F0x3008200x300820AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_40x3008240x3008FF0x3009000x300900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_40x3009040x300904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_40x3009080x300908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_40x30090C0x30090CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_40x3009100x300910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_40x3009140x300914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_40x3009180x300918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_40x30091C0x30091F0x3009200x300920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_40x3009240x3009FF0x300A000x300A00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_50x300A040x300A04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_50x300A080x300A08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_50x300A0C0x300A0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_50x300A100x300A10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_50x300A140x300A14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_50x300A180x300A18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_50x300A1C0x300A1F0x300A200x300A20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_50x300A240x300AFF0x300B000x300B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_50x300B040x300B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_50x300B080x300B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_50x300B0C0x300B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_50x300B100x300B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_50x300B140x300B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_50x300B180x300B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_50x300B1C0x300B1F0x300B200x300B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_50x300B240x300BFF0x300C000x300C00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_60x300C040x300C04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_60x300C080x300C08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_60x300C0C0x300C0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_60x300C100x300C10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_60x300C140x300C14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_60x300C180x300C18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_60x300C1C0x300C1F0x300C200x300C20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_60x300C240x300CFF0x300D000x300D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_60x300D040x300D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_60x300D080x300D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_60x300D0C0x300D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_60x300D100x300D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_60x300D140x300D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_60x300D180x300D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_60x300D1C0x300D1F0x300D200x300D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_60x300D240x300DFF0x300E000x300E00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_70x300E040x300E04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_70x300E080x300E08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_70x300E0C0x300E0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_70x300E100x300E10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_70x300E140x300E14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_70x300E180x300E18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_70x300E1C0x300E1F0x300E200x300E20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_70x300E240x300EFF0x300F000x300F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_70x300F040x300F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_70x300F080x300F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_70x300F0C0x300F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_70x300F100x300F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_70x300F140x300F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_70x300F180x300F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_70x300F1C0x300F1F0x300F200x300F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_70x300F240x300FFF0x3010000x301000AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_80x3010040x301004AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_80x3010080x301008AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_80x30100C0x30100CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_80x3010100x301010AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_80x3010140x301014AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_80x3010180x301018AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_80x30101C0x30101F0x3010200x301020AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_80x3010240x3010FF0x3011000x301100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_80x3011040x301104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_80x3011080x301108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_80x30110C0x30110CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_80x3011100x301110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_80x3011140x301114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_80x3011180x301118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_80x30111C0x30111F0x3011200x301120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_80x3011240x3011FF0x3012000x301200AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_90x3012040x301204AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_90x3012080x301208AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_90x30120C0x30120CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_90x3012100x301210AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_90x3012140x301214AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_90x3012180x301218AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_90x30121C0x30121F0x3012200x301220AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_90x3012240x3012FF0x3013000x301300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_90x3013040x301304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_90x3013080x301308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_90x30130C0x30130CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_90x3013100x301310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_90x3013140x301314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_90x3013180x301318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_90x30131C0x30131F0x3013200x301320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_90x3013240x3013FF0x3014000x301400AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_100x3014040x301404AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_100x3014080x301408AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_100x30140C0x30140CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_100x3014100x301410AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_100x3014140x301414AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_100x3014180x301418AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_100x30141C0x30141F0x3014200x301420AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_100x3014240x3014FF0x3015000x301500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_100x3015040x301504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_100x3015080x301508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_100x30150C0x30150CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_100x3015100x301510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_100x3015140x301514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_100x3015180x301518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_100x30151C0x30151F0x3015200x301520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_100x3015240x3015FF0x3016000x301600AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_110x3016040x301604AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_110x3016080x301608AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_110x30160C0x30160CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_110x3016100x301610AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_110x3016140x301614AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_110x3016180x301618AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_110x30161C0x30161F0x3016200x301620AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_110x3016240x3016FF0x3017000x301700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_110x3017040x301704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_110x3017080x301708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_110x30170C0x30170CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_110x3017100x301710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_110x3017140x301714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_110x3017180x301718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_110x30171C0x30171F0x3017200x301720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_110x3017240x3017FF0x3018000x301800AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_120x3018040x301804AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_120x3018080x301808AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_120x30180C0x30180CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_120x3018100x301810AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_120x3018140x301814AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_120x3018180x301818AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_120x30181C0x30181F0x3018200x301820AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_120x3018240x3018FF0x3019000x301900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_120x3019040x301904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_120x3019080x301908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_120x30190C0x30190CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_120x3019100x301910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_120x3019140x301914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_120x3019180x301918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_120x30191C0x30191F0x3019200x301920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_120x3019240x3019FF0x301A000x301A00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_130x301A040x301A04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_130x301A080x301A08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_130x301A0C0x301A0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_130x301A100x301A10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_130x301A140x301A14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_130x301A180x301A18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_130x301A1C0x301A1F0x301A200x301A20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_130x301A240x301AFF0x301B000x301B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_130x301B040x301B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_130x301B080x301B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_130x301B0C0x301B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_130x301B100x301B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_130x301B140x301B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_130x301B180x301B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_130x301B1C0x301B1F0x301B200x301B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_130x301B240x301BFF0x301C000x301C00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_140x301C040x301C04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_140x301C080x301C08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_140x301C0C0x301C0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_140x301C100x301C10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_140x301C140x301C14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_140x301C180x301C18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_140x301C1C0x301C1F0x301C200x301C20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_140x301C240x301CFF0x301D000x301D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_140x301D040x301D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_140x301D080x301D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_140x301D0C0x301D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_140x301D100x301D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_140x301D140x301D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_140x301D180x301D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_140x301D1C0x301D1F0x301D200x301D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_140x301D240x301DFF0x301E000x301E00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_150x301E040x301E04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_150x301E080x301E08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_150x301E0C0x301E0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_150x301E100x301E10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_150x301E140x301E14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_150x301E180x301E18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_150x301E1C0x301E1F0x301E200x301E20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_150x301E240x301EFF0x301F000x301F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_150x301F040x301F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_150x301F080x301F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_150x301F0C0x301F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_150x301F100x301F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_150x301F140x301F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_150x301F180x301F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_150x301F1C0x301F1F0x301F200x301F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_150x301F240x3020FF0x3021000x302100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_160x3021040x302104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_160x3021080x302108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_160x30210C0x30210CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_160x3021100x302110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_160x3021140x302114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_160x3021180x302118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_160x30211C0x30211F0x3021200x302120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_160x3021240x3022FF0x3023000x302300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_170x3023040x302304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_170x3023080x302308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_170x30230C0x30230CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_170x3023100x302310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_170x3023140x302314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_170x3023180x302318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_170x30231C0x30231F0x3023200x302320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_170x3023240x3024FF0x3025000x302500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_180x3025040x302504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_180x3025080x302508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_180x30250C0x30250CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_180x3025100x302510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_180x3025140x302514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_180x3025180x302518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_180x30251C0x30251F0x3025200x302520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_180x3025240x3026FF0x3027000x302700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_190x3027040x302704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_190x3027080x302708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_190x30270C0x30270CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_190x3027100x302710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_190x3027140x302714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_190x3027180x302718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_190x30271C0x30271F0x3027200x302720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_190x3027240x3028FF0x3029000x302900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_200x3029040x302904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_200x3029080x302908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_200x30290C0x30290CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_200x3029100x302910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_200x3029140x302914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_200x3029180x302918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_200x30291C0x30291F0x3029200x302920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_200x3029240x302AFF0x302B000x302B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_210x302B040x302B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_210x302B080x302B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_210x302B0C0x302B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_210x302B100x302B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_210x302B140x302B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_210x302B180x302B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_210x302B1C0x302B1F0x302B200x302B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_210x302B240x302CFF0x302D000x302D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_220x302D040x302D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_220x302D080x302D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_220x302D0C0x302D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_220x302D100x302D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_220x302D140x302D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_220x302D180x302D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_220x302D1C0x302D1F0x302D200x302D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_220x302D240x302EFF0x302F000x302F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_230x302F040x302F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_230x302F080x302F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_230x302F0C0x302F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_230x302F100x302F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_230x302F140x302F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_230x302F180x302F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_230x302F1C0x302F1F0x302F200x302F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_230x302F240x3030FF0x3031000x303100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_240x3031040x303104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_240x3031080x303108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_240x30310C0x30310CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_240x3031100x303110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_240x3031140x303114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_240x3031180x303118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_240x30311C0x30311F0x3031200x303120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_240x3031240x3032FF0x3033000x303300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_250x3033040x303304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_250x3033080x303308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_250x30330C0x30330CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_250x3033100x303310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_250x3033140x303314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_250x3033180x303318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_250x30331C0x30331F0x3033200x303320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_250x3033240x3034FF0x3035000x303500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_260x3035040x303504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_260x3035080x303508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_260x30350C0x30350CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_260x3035100x303510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_260x3035140x303514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_260x3035180x303518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_260x30351C0x30351F0x3035200x303520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_260x3035240x3036FF0x3037000x303700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_270x3037040x303704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_270x3037080x303708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_270x30370C0x30370CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_270x3037100x303710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_270x3037140x303714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_270x3037180x303718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_270x30371C0x30371F0x3037200x303720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_270x3037240x3038FF0x3039000x303900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_280x3039040x303904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_280x3039080x303908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_280x30390C0x30390CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_280x3039100x303910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_280x3039140x303914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_280x3039180x303918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_280x30391C0x30391F0x3039200x303920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_280x3039240x303AFF0x303B000x303B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_290x303B040x303B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_290x303B080x303B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_290x303B0C0x303B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_290x303B100x303B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_290x303B140x303B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_290x303B180x303B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_290x303B1C0x303B1F0x303B200x303B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_290x303B240x303CFF0x303D000x303D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_300x303D040x303D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_300x303D080x303D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_300x303D0C0x303D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_300x303D100x303D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_300x303D140x303D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_300x303D180x303D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_300x303D1C0x303D1F0x303D200x303D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_300x303D240x303EFF0x303F000x303F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_310x303F040x303F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_310x303F080x303F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_310x303F0C0x303F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_310x303F100x303F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_310x303F140x303F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_310x303F180x303F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_310x303F1C0x303F1F0x303F200x303F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_310x303F240x31FF230x31FF240x37FFFF0x3800000x381123AXI_Slave.PF0_DMA_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP0x3800000x380000AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFF0x3800040x3800070x3800080x380008AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFF0x38000C0x38000CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFF0x3800100x380010AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFF0x3800140x3800170x3800180x380018AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF0x38001C0x38001CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800200x38002B0x38002C0x38002CAXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFF0x3800300x380030AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFF0x3800340x3800370x3800380x380038AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF0x38003C0x38003CAXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800400x38004B0x38004C0x38004CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFF0x3800500x3800530x3800540x380054AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFF0x3800580x380058AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFF0x38005C0x38005CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFF0x3800600x380060AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFF0x3800640x380064AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFF0x3800680x380068AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFF0x38006C0x38006CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFF0x3800700x380070AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFF0x3800740x380074AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFF0x3800780x380078AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFF0x38007C0x38007CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFF0x3800800x38008F0x3800900x380090AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFF0x3800940x38009F0x3800A00x3800A0AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFF0x3800A40x3800A70x3800A80x3800A8AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFF0x3800AC0x3800ACAXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFF0x3800B00x3800B30x3800B40x3800B4AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFF0x3800B80x3800B8AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFF0x3800BC0x3800C30x3800C40x3800C4AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFF0x3800C80x3800CB0x3800CC0x3800CCAXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFF0x3800D00x3800D0AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFF0x3800D40x3800D4AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFF0x3800D80x3800D8AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFF0x3800DC0x3800DCAXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFF0x3800E00x3800E0AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFF0x3800E40x3800E4AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFF0x3800E80x3800E8AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFF0x3800EC0x3801070x3801080x380108AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF0x38010C0x38010CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801100x3801170x3801180x380118AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF0x38011C0x38011CAXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801200x3801FF0x3802000x380200AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_00x3802040x380204AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_00x3802080x380208AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_00x38020C0x38020CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_00x3802100x380210AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_00x3802140x380214AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_00x3802180x380218AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_00x38021C0x38021CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_00x3802200x380220AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_00x3802240x3802FF0x3803000x380300AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_00x3803040x380304AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_00x3803080x380308AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_00x38030C0x38030CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_00x3803100x380310AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_00x3803140x380314AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_00x3803180x380318AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_00x38031C0x38031CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_00x3803200x380320AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_00x3803240x3803FF0x3804000x380400AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_10x3804040x380404AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_10x3804080x380408AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_10x38040C0x38040CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_10x3804100x380410AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_10x3804140x380414AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_10x3804180x380418AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_10x38041C0x38041CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_10x3804200x380420AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_10x3804240x3804FF0x3805000x380500AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_10x3805040x380504AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_10x3805080x380508AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_10x38050C0x38050CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_10x3805100x380510AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_10x3805140x380514AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_10x3805180x380518AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_10x38051C0x38051CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_10x3805200x380520AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_10x3805240x3805FF0x3806000x380600AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_20x3806040x380604AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_20x3806080x380608AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_20x38060C0x38060CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_20x3806100x380610AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_20x3806140x380614AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_20x3806180x380618AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_20x38061C0x38061CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_20x3806200x380620AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_20x3806240x3806FF0x3807000x380700AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_20x3807040x380704AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_20x3807080x380708AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_20x38070C0x38070CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_20x3807100x380710AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_20x3807140x380714AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_20x3807180x380718AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_20x38071C0x38071CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_20x3807200x380720AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_20x3807240x3807FF0x3808000x380800AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_30x3808040x380804AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_30x3808080x380808AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_30x38080C0x38080CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_30x3808100x380810AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_30x3808140x380814AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_30x3808180x380818AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_30x38081C0x38081CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_30x3808200x380820AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_30x3808240x3808FF0x3809000x380900AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_30x3809040x380904AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_30x3809080x380908AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_30x38090C0x38090CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_30x3809100x380910AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_30x3809140x380914AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_30x3809180x380918AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_30x38091C0x38091CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_30x3809200x380920AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_30x3809240x381123groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDRPF0_TYPE1_HDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr17050x0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDRPCI-Compatible Configuration Space Header Type1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BAR0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BAR1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REGTYPE1_DEV_ID_VEND_ID_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr660x0R0xeb011e0aPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REGDevice ID and Vendor ID Register.falsefalsefalsefalseVENDOR_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49Vendor ID.The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x1e0aRDEVICE_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65Device ID.The Device ID register identifies the particular Function. This identifier is allocated by the vendor.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160xeb01RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REGTYPE1_STATUS_COMMAND_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr4160x4R/W0x00100000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REGStatus and Command Register.falsefalsefalsefalseIO_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90IO Space Enable.This bit controls a Function's response to I/O Space accesses received on its primary side. - When set, the Function is enabled to decode the address and further process I/O Space accesses. - When clear, all received I/O accesses are caused to be handled as Unsupported Requests.You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar =0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: !has_io_bar ? RO : RW 000x0R/WMSEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr111Memory Space Enable.This bit controls a Function's response to Memory Space accesses received on its primary side. - When set, the Function is enabled to decode the address and further process Memory Space accesses. - When clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar =0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: !has_mem_bar ? RO : RW 110x0R/WBMEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr129Bus Master Enable.This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction.When this bit is 0b, Memory and I/O Requests received at a RootPort must be handled as Unsupported Requests (UR)For Non-Posted Requests a Completion with UR completion status must be returned.This bit does not affect forwarding of Completions in either the Upstream or Downstream direction.The forwarding of Requests other than Memory or I/O Requests is not controlled by this bit.220x0R/WSCOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr140Special Cycle Enable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.330x0RMWI_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr156Memory Write and Invalidate.This bit was originally described in the PCI Local Bus Specification and thePCI-to-PCI Bridge Architecture Specification. Its functionality does not applyto PCI Express. The controller hardwires this bit to 0b. For PCI Express to PCI/PCI-X Bridges, refer to the PCI Express to PCI/PCI-X Bridge Specification for requirements for this register.440x0RVGAPSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr168VGA Palette Snoop.This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.550x0RPERRENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr179Parity Error Response.This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register.For more details see the "Error Registers" section of the PCI Express Base Specification.660x0R/WIDSELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr190IDSEL Stepping/Wait Cycle Control.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.770x0RSERRENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr209SERR# Enable.When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control register. For more details see the "Error Registers" section of the PCI Express Base Specification.In addition, this bit controls transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error Messages forwarded from the secondary interface. This bit does not affect the transmission of forwarded ERR_COR messages.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr217Reserved for future use.990x0RINT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr242Interrupt Disable.Controls the ability of a Function to generate INTx emulation interrupts. When set, Functions are prevented from asserting INTx interrupts.Note: - Any INTx emulation interrupts already asserted by the Function must be deasserted when this bit is set. INTx interrupts use virtual wires that must, if asserted, be deasserted using the appropriate Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected. - For Functions that generate INTx interrupts on their own behalf, this bit is required. This bit has no effect on interrupts forwarded from the secondary side. For Functions that do not generate INTx interrupts on their own behalf this bit is optional. If this bit is not implemented, the controller hardwires it to 0b.10100x0R/WRESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr251Reserved.15110x00R--16160x0rRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr259Reserved for future use.18170x0RINT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr278Interrupt Status.When set, indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit.Setting the Interrupt Disable bit has no effect on the state of this bit.For Functions that do not generate INTx interrupts, the controller hardwiresthis bit to 0b.19190x0RCAP_LISTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr291Capabilities List.Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.20200x1RFAST_66MHZ_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30266 MHz Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.21210x0RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr310Reserved for future use.22220x0RFAST_B2B_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr321Fast Back-to-Back Transactions Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.23230x0RMASTER_DPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr337Master Data Parity Error.This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a Poisoned Request upstreamIf the Parity Error Response bit is 0b, this bit is never set.24240x0R/W1CDEV_SEL_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr348DEVSEL Timing.This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b.26250x0RSIGNALED_TARGET_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr361Signaled Target Abort.This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side.27270x0R/W1CRCVD_TARGET_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr375Received Target Abort.This bit is set when a Requester receives a Completion with Completer AbortCompletion status. The bit is set when the Completer Abort is received by aFunction's primary side.28280x0R/W1CRCVD_MASTER_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr388Received Master Abort.This bit is set when a Requester receives a Completion with Unsupported Request Completion status.The bit is set when the Unsupported Request is received by a Function's primary side.29290x0R/W1CSIGNALED_SYS_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr400Signaled System Error.This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR# Enable bit in the Command register is 1b.30300x0R/W1CDETECTED_PARITY_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr415Detected Parity Error.This bit is set by a Function whenever it receives a Poisoned TLP, regardlessof the state the Parity Error Response bit in the Command register. The bit isset when the Poisoned TLP is received by a Function's primary side.31310x0R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REGTYPE1_CLASS_CODE_REV_ID_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr4970x8R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REGClass Code and Revision ID Register.falsefalsefalsefalseREVISION_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr438Revision ID.The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x01RPROGRAM_INTERFACEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr458Programming Interface.This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function.Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1580x00RSUBCLASS_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr477Sub-Class Code.Specifies a base class sub-class, which identifies more specifically the operation of the Function.Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23160x00RBASE_CLASS_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr496Base Class Code.A code that broadly classifies the type of operation the Function performs.Encodings for base class, are provided in the PCI Code and ID AssignmentSpecification. All unspecified encodings are reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGTYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr6000xCR/W0x00010000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGBIST, Header Type, Latency Timer, and Cache Line Size Register.falsefalsefalsefalseCACHE_LINE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr516Cache Line Size.The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express device behavior.700x00R/WLATENCY_MASTER_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr530Latency Timer.This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.1580x00RHEADER_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr547Header Layout.This field identifies the layout of the second part of the predefined header.The controller uses 000 0001b encoding.The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical Specification and is used in previous versions of the programming model. Careful consideration should be given to any attempt to repurpose it.22160x01RMULTI_FUNCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr567Multi-Function Device. - When set, indicates that the device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear, software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure.Except where stated otherwise, it is recommended that this bit be set if thereare multiple Functions, and clear if there is only one Function.Note: This register field is sticky.23230x0RBISTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr599BIST.This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link.Bit descriptions: - [31]: BIST Capable. When set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST. If BIST Capable is set, set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been set. Writing this bit to 0b has no effect. The controller hardwires this bit to 0b if BIST Capable is clear. - [29:28]: Reserved. - [27:24]: Completion Code. This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BAR0_REGBAR0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr7030x10R/W0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_BAR0_REGBAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR0_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr635BAR0 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR0_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr663BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR0_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr685BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR0_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr702BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BAR1_REGBAR1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr8000x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_BAR1_REGBAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR1_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr736BAR1 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR1_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr762BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR1_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr782BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR1_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr799BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGSEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr8540x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGSecondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register.falsefalsefalsefalsePRIM_BUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr813Primary Bus Number.This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software.700x00R/WSEC_BUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr828Secondary Bus Number.The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge uses this register to determine when to respond to and convert a Type 1 configuration transaction on the primary interface into a Type 0 transaction on the secondary interface.1580x00R/WSUB_BUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr843Subordinate Bus Number.The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The bridge uses this register in conjunction with the Secondary Bus Number register to determine when to respond to and pass on a Type 1 configuration transaction on the primary interface to the secondary interface.23160x00R/WSEC_LAT_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr853Secondary Latency Timer.This register does not apply to PCI Express. The controller hardwires it to 00h.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REGSEC_STAT_IO_LIMIT_IO_BASE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr10970x1CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REGSecondary Status, and I/O Limit and Base Register.The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. If a bridge does not implement an I/O address range, then both the I/O Limit and I/O Base registers must be implemented as read-only registers that return zero when read. If a bridge supports an I/O address range, then these registers must be initialized by configuration software so default states are not specified.falsefalsefalsefalseIO_DECODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr901I/O Addressing Encode (IO Base Address)This bit encodes the IO addressing capability of the bridge.IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address decoding, the bridge assumes that the upper 16 address bits, Address[31:16], of the I/O base address (not implemented in I/O base register) are zero.Note: The bridge must still perform a full 32-bit decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case, the I/O address range supported by the bridge will be restricted to the first 64 KB of I/O Space (0000 0000h to 0000 FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Base Upper 16 Bits hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Base address. In this case, system configuration software is permitted to locate the I/O address range supported by the bridge anywhere in the 4-GB I/O Space.Note: The 4-KB alignment and granularity restrictions still apply when the bridge supports 32-bit I/O addressing.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 000x0RIO_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr909Reserved.310x0RIO_BASEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr922I/O Base Address.These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding, the bridge assumes that the lower 12 address bits, address[11:0], of the I/O base address (not implemented in the I/O Base register) are zero.740x0R/WIO_DECODE_BIT8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr957I/O Addressing Encode (IO Limit Address).This bit encodes the IO addressing capability of the bridge.IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address decoding, the bridge assumes that the upper 16 address bits, Address[31:16], of the I/O limit address (not implemented in I/O Limit register) are zero.Note: The bridge must still perform a full 32-bit decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case, the I/O address range supported by the bridge will be restricted to the first 64 KB of I/O Space (0000 0000h to 0000 FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Limit Upper 16 Bits hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Limit address. In this case, system configuration software is permitted to locate the I/O address range supported by the bridge anywhere in the 4-GB I/O Space.Note: The 4-KB alignment and granularity restrictions still apply when the bridge supports 32-bit I/O addressing.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 88RIO_RESERV1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr966Reserved.1190x0RIO_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr987I/O Limit Address.These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding, the bridge assumes that the lower 12 address bits, address[11:0], of the I/O limit address (not implemented in the I/O Limit register) are FFFh.The I/O Limit register can be programmed to a smaller value than the I/O Base register, if there are no I/O addresses on the secondary side of the bridge. In this case, the bridge will not forward any I/O transactions from the primary bus to the secondary and will forward all I/O transactions from the secondary bus to the primary bus.15120x0R/WSEC_STAT_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr996Reserved.22160x00RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1004Reserved for future use.23230x0RSEC_STAT_MDPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1021Master Data Parity Error.This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set, and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream - Port transmits a Poisoned Request DownstreamIf the Parity Error Response Enable bit is clear, this bit is never set.24240x0R/W1CRSVDP_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1029Reserved for future use.26250x0RSEC_STAT_SIG_TRGT_ABRTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1043Signaled Target Abort.This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error.27270x0R/W1CSEC_STAT_RCVD_TRGT_ABRTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1057Received Target Abort.This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status.28280x0R/W1CSEC_STAT_RCVD_MSTR_ABRTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1071Received Master Abort.This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status.29290x0R/W1CSEC_STAT_RCVD_SYS_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1083Received System Error.This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message.30300x0R/W1CSEC_STAT_DPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1096Detected Parity Error.This bit is set by a Function when a Poisoned TLP is received by its secondary side, regardless of the state the Parity Error Response Enable bit in the Bridge Control register.31310x0R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REGMEM_LIMIT_MEM_BASE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr11550x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REGMemory Limit and Base Register.The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there is no prefetchable memory space, and there is no memory-mapped space on the secondary side of the bridge, then the bridge will not forward any memory transactions from the primary bus to the secondary bus and will forward all memory transactions from the secondary bus to the primary bus.falsefalsefalsefalseMEM_BASE_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1117Reserved.300x0RMEM_BASEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1129Memory Base Address.These bits correspond to the upper 12 address bits, Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the lower 20 address bits, Address[19:0], of the memory base address (not implemented in the Memory Base register) are zero.1540x000R/WMEM_LIMIT_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1137Reserved.19160x0RMEM_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1154Memory Limit Address.These bits correspond to the upper 12 address bits, Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the lower 20 address bits, Address[19:0], of the memory limit address (not implemented in the Memory Limit register) are F FFFFh.The Memory Limit register must be programmed to a smaller value than the Memory Base register if there is no memory-mapped address space on the secondary side of the bridge.31200x000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REGPREF_MEM_LIMIT_PREF_MEM_BASE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr12800x24R/W0x00010001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REGPrefetchable Memory Limit and Base Register.The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported, as defined in PCI-to-PCI Bridge Architecture Specification. The Prefetchable Memory Limit and Prefetchable Memory Base registers are optional. They define a prefetchable memory address range which is used by the bridge to determine when to forward memory transactions from one interface to the other (see the PCI-to-PCI Bridge Architecture Specification for additional details).falsefalsefalsefalsePREF_MEM_DECODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1196Prefetchable Memory Base Decode.This bit encodes whether or not the bridge supports 64-bitaddresses.Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable memory address range, or if there is no prefetchable memory address range, then the configuration parameter MEM_DECODE_64_0 must be changed to 0.The value of PREF_MEM_DECODE indicates the following: - 0b: Indicates that the bridge supports only 32 bit addresses. - 1b: Indicates that the bridge supports 64 bit addresses. Prefetchable Base Upper 32 Bits registers holds the rest of the 64-bit prefetchable base address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.000x1RPREF_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1205Reserved.310x0RPREF_MEM_BASEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1226Prefetchable Memory Base Address.If the Prefetchable Memory Base register indicates support for 32-bit addressing, then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read.If the Prefetchable Memory Base register indicates support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read/write register which must be initialized by configuration software.If a 64-bit prefetchable memory address range is supported, the Prefetchable Base Upper 32 Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address range.1540x000R/WPREF_MEM_LIMIT_DECODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1249Prefetchable Memory Limit Decode.This bit encodes whether or not the bridge supports 64-bitaddresses.Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit.The value of PREF_MEM_LIMIT_DECODE indicates the following: -0b: Indicates that the bridge supports only 32 bit addresses. -1b: Indicates that the bridge supports 64 bit addresses. Prefetchable Limit Upper 32 Bits registers holds the rest of the 64-bit prefetchable limit address.16160x1RPREF_RESERV1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1257Reserved.19170x0RPREF_MEM_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1279Prefetchable Memory Limit Address.If the Prefetchable Memory Limit register indicates support for 32-bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read.If the Prefetchable Memory Limit registers indicate support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read/write register which must be initialized by configuration software.If a 64-bit prefetchable memory address range is supported, the Prefetchable Limit Upper 32 Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit limit addresses which specify the prefetchable memory address range.31200x000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REGPREF_BASE_UPPER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr13090x28R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_PREF_BASE_UPPER_REGPrefetchable Base Upper 32 Bits Register.The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register.falsefalsefalsefalsePREF_MEM_BASE_UPPERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1308Prefetchable Base Upper 32 Bit.If the Prefetchable Memory Base register indicates support for 32-bit addressing, then this register is implemented as read-only register that returns zero when read.If the Prefetchable Memory Base register indicate support for 64-bit addressing, then this register is implemented as read/write register which must be initialized by configuration software.This register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address range.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PREF_MEM_LIMIT_PREF_MEM_BASE_REG.PREF_MEM_DECODE ? RW : RO 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REGPREF_LIMIT_UPPER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr13350x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REGPrefetchable Limit Upper 32 Bits Register.The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register.falsefalsefalsefalsePREF_MEM_LIMIT_UPPERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1334Prefetchable Limit Upper 32 Bit.If the Prefetchable Memory Limit register indicate support for 64-bit addressing, then this register is implemented as read/write register which must be initialized by configuration software.This register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address range.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PREF_MEM_LIMIT_PREF_MEM_BASE_REG.PREF_MEM_DECODE ? RW : RO 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REGIO_LIMIT_UPPER_IO_BASE_UPPER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr13890x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REGI/O Limit and Base Upper 16 Bits Register.The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers.falsefalsefalsefalseIO_BASE_UPPERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1365I/O Base Upper 16 Bits.If the I/O Base register indicates support for 16-bit I/O address decoding, then this register is implemented as a read-only register which return zero when read.If the I/O base register indicates support for 32-bit I/O addressing, then this register must be initialized by configuration software.If 32-bit I/O address decoding is supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the 32-bit base address, that specify the I/O address range. See the PCI-to-PCI Bridge Architecture Specification for additional details.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: SEC_STAT_IO_LIMIT_IO_BASE_REG.IO_DECODE ? RW : RO 1500x0000RIO_LIMIT_UPPERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1388I/O Limit Upper 16 Bits.If the I/O Limit register indicates support for 16-bit I/O address decoding, then this register is implemented as a read-only register which return zero when read.If the I/O Limit register indicates support for 32-bit I/O addressing, then this register must be initialized by configuration software.If 32-bit I/O address decoding is supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the 32-bit limit address, that specify the I/O address range. See the PCI-to-PCI Bridge Architecture Specification for additional details).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: SEC_STAT_IO_LIMIT_IO_BASE_REG.IO_DECODE ? RW : RO 31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REGTYPE1_CAP_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr14260x34R0x00000040PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REGCapabilities Pointer Register.falsefalsefalsefalseCAP_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1418Capabilities Pointer.This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure, this register must point to a valid capability structure and either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are Reserved and must be set to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x40RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1425Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REGTYPE1_EXP_ROM_BASE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr14890x38R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REGExpansion ROM Base Address Register.This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.falsefalsefalsefalseROM_BAR_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1459Expansion ROM Enable.This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b, the Function's expansion ROM address space is disabled. When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register. The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1467Reserved for future use.1010x000REXP_ROM_BASE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1488Expansion ROM Base Address.Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 31110x000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REGBRIDGE_CTRL_INT_PIN_INT_LINE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr17040x3CR/W0x000001ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REGBridge Control, Interrupt Pin, and Interrupt Line Register.falsefalsefalsefalseINT_LINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1507Interrupt Line.The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.700xffR/WINT_PINPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1543Interrupt PIN.The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses.Valid values are: - 01h, 02h, 03h, and 04h: map to legacy interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: indicates that the Function uses no legacy interrupt Message(s). - 05h through FFh: Reserved.PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth.For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x01RPEREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1553Parity Error Response Enable.This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register.16160x0R/WSERR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1562SERR# Enable.This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL from secondary to primary.17170x0R/WISA_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1587ISA Enable.Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions will be forwarded if they address the last 768 bytes in each 1-KB block.The following actions are taken based on the value of the ISA_EN bit: - 0b: Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit registers - 1b: Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1-KB block.18180x0R/WVGA_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1637VGA Enable.Modifies the response by the bridge to VGA compatible addresses.If the VGA Enable bit is set, the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and, conversely, block the forwarding of these addresses from the secondary to primary interface): - Memory accesses in the range 000A 0000h to 000B FFFFh - I/O addresses in the first 64 KB of the I/O address space (Address[31:16] are 0000h) where Address[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases determined by the setting of VGA 16-bit Decode )If the VGA Enable bit is set, forwarding of these accesses is independent of the I/O address range and memory address ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the Prefetchable Memory Base and Limit registers of the bridge. (Forwarding of these accesses is also independent of the setting of the ISA Enable bit (in the Bridge Control register) when the VGA Enable bit is set. Forwarding of these accesses is qualified by the I/O Space Enable and Memory Space Enable bits in the Command register.)The following actions are taken based on the value of the VGA_EN bit: - 0b: Do not forward VGA compatible memory and I/O addresses from the primary to the secondary interface (addresses defined above) unless they are enabled for forwarding by the defined I/O and memory address ranges - 1b: Forward VGA compatible memory and I/O addresses (addresses defined above) from the primary interface to the secondary interface (if the I/O Space Enable and Memory Space Enable bits are set) independent of the I/O and memory address ranges and independent of the ISA Enable bitFor Functions that do not support VGA, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 19190x0RVGA_16B_DECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1660VGA 16 bit decode.This bit only has meaning if VGA Enable bit is set.This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary to secondary.The following actions are taken based on the value of the VGA_16B_DEC bit: - 0b: Execute 10-bit address decodes on VGA I/O accesses - 1b: Execute 16-bit address decodes on VGA I/O accessesFor Functions that do not support VGA, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 20200x0RMSTR_ABORT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1678Master Abort Mode.This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21210x0RSBRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1695Secondary Bus Reset.Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor first-access-following-reset timing requirements, unless the Readiness Notifications mechanism is used or if the Immediate Readiness bit in the relevant Function's Status Register register is set.Port configuration registers must not be changed, except as required to update Port status.22220x0R/WBRIDGE_CTRL_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1703Reserved.31230x000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAPPF0_PM_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr20910x40R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAPPF PCI Power Management Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CON_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGCAP_ID_NXT_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr18970x0R0x03c35001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAP_CAP_ID_NXT_PTR_REGPower Management Capabilities Register.falsefalsefalsefalsePM_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1724Capability ID.This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h.700x01RPM_NEXT_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1741Next Capability Pointer.This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list, this field is set to 00h.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x50RPM_SPEC_VERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1758Version.This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0>.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.18160x3RPME_CLKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1769PME Clock.Does not apply to PCI Express, the controller hardwires it to 0b.Note: This register field is sticky.19190x0R--20200x0rDSIPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1788Device Specific Initialization.The DSI bit indicates whether special initialization of this function is required.When set, indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized state.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x0RAUX_CURRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1821Aux_Current.This 3 bit field reports the Vaux auxiliary current requirements for the function.If this function implements the Data Register, the controller hardwires this field to 000b.If PME_Support is 0 xxxxb (PME assertion from D3cold is not supported), the controller hardwires this field to 0000b.For functions where PME_Support is 1 xxxxb (PME assertion from D3cold is supported), and which do not implement the Data field, the following encodings apply: - b111 375mA Vaux Max. Current Required - b110 320mA Vaux Max. Current Required - b101 270mA Vaux Max. Current Required - b100 220mA Vaux Max. Current Required - b011 160mA Vaux Max. Current Required - b010 100mA Vaux Max. Current Required - b001 55mA Vaux Max. Current Required - b000 0 self poweredNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.24220x7RD1_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1837D1_Support.If this bit is set, this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RD2_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1853D2_Support.If this bit is set, this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26260x0RPME_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1896PME_Support.This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages.A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. - bit(27) X XXX1b - PME can be generated from D0 - bit(28) X XX1Xb - PME can be generated from D1 - bit(29) X X1XXb - PME can be generated from D2 - bit(30) X 1XXXb - PME can be generated from D3hot - bit(31) 1 XXXXb - PME can be generated from D3coldBit 31 (PME can be asserted from D3cold) represents a special case. Functions that set this bit require some sort of auxiliary power source. Implementation specific mechanisms are recommended to validate that the power source is available before setting this bit.Each bit that corresponds to a supported D-state must be set for PCI-PCI Bridge structures representing Ports on Root Complexes/Switches to indicate that the Bridge will forward PME Messages. Bit 31 must only be set if the Port is still able to forward PME Messages when main power is not available.The read value from this field is the write value && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are fields in this register.The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3127RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PM_CAP.CON_STATUS_REGCON_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr20900x4R/W0x00000008PE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAP_CON_STATUS_REGPower Management Control and Status Register.This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs.falsefalsefalsefalsePOWER_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1941PowerState.This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below.You can write to this register; however, the read-back value is the actual power state, not the write value. If you attempt to write an unsupported, optional state to this field, the write operation completes normally; however, the data is discarded and no state change occurs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 10R/WfalsetruefalseD00x0D0 power stateD10x1D1 power stateD20x2D2 power stateD3hot0x3D3hot D3hot power stateRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1949Reserved for future use.220x0RNO_SOFT_RSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1975No_Soft_Reset.This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set, this transition preserves internal function state. The function is in D0Active and no additional software intervention is required. - When clear, this transition results in undefined internal function state.Regardless of this bit, functions that transition from D3hot to D0 by Fundamental Reset will return to D0Uninitialized with only PME context preserved if PME is supported and enabled.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.330x1RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr1983Reserved for future use.740x0RPME_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2004PME_En. - When set, the function is permitted to generate a PME. - When clear, the function is not permitted to generate a PME.If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is available this bit is RWS and the bit is not modified by Conventional Reset or FLR.If PME_Support is 0 xxxxb, this field is not sticky (RW).If PME_Support is 0 0000b, the controller hardwires this bit to 0b.Note: This register field is sticky.88R/WDATA_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2016Data_Select.This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented, this field must be hardwired to 0000b.1290x0RDATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2030Data_Scale.This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details, see 7.5.2.3 section of PCI Express Base Specification.14130x0RPME_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2049PME_Status.This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit.If PME_Support bit 31 of the Power Management Capabilities register is clear, this bit is permitted to be hardwired to 0b.Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this register value is not modified by Conventional Reset or FLR.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2057Reserved for future use.21160x00RB2_B3_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2067B2B3 Support for D3hot.For a description of this standard PCIe register field, see the PCI Express Base Specification.22220x0RBUS_PWR_CLK_CON_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2077Bus Power/Clock Control Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.23230x0RDATA_REG_ADD_INFOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2089Data.This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field.31240x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAPPF0_MSI_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr24860x50R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAPPF MSI Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr22690x0R/W0x038a7005PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REGMSI Capability Header and Message Control Register.falsefalsefalsefalsePCI_MSI_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2109Capability ID.Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure.700x05RPCI_MSI_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2126Next Capability Pointer.This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x70RPCI_MSI_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2143MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear, the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function's service request. For more details on control of INTx interrupts, see section 7.5.1.1 of PCI Express Base Specification. - If clear, the function is prohibited from using MSI to request service.16160x0R/WPCI_MSI_MULTIPLE_MSG_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2169Multiple Message Capable.System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors, it requests four by initializing this field to 010b). The encoding is defined as: - 000b: 1 vector requested - 001b: 2 vectors requested - 010b: 4 vectors requested - 011b: 8 vectors requested - 100b: 16 vectors requested - 101b: 32 vectors requested - 110b: Reserved - 111b: ReservedNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19170x5RPCI_MSI_MULTIPLE_MSG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2194Multiple Message Enable.Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a function requests four vectors (indicated by a Multiple Message Capable encoding of 010b), system software can allocate either four, two, or one vector by writing a 010b, 001b, or 000b to this field, respectively. When MSI is enabled, a function will be allocated at least 1 vector. The encoding is defined as: - 000b: 1 vector allocated - 001b: 2 vectors allocated - 010b: 4 vectors allocated - 011b: 8 vectors allocated - 100b: 16 vectors allocated - 101b: 32 vectors allocated - 110b: Reserved - 111b: Reserved22200x0R/WPCI_MSI_64_BIT_ADDR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr221464 bit address capable. - If set, the function is capable of sending a 64-bit message address. - If clear, the function is not capable of sending a 64-bit message address.This bit must be set if the function is a PCI Express Endpoint.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.23230x1RPCI_PVM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2227Per-Vector Masking Capable. - If set, the function supports MSI Per-Vector Masking. - If clear, the function does not support MSI Per-Vector Masking.This bit must be set if the function is a PF or VF within an SR-IOV Device.24240x1RPCI_MSI_EXT_DATA_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2244Extended Message Data Capable. - If set, the function is capable of providing Extended Message Data. - If clear, the function does not support providing Extended Message Data.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RPCI_MSI_EXT_DATA_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2260Extended Message Data Enable. - If set, the function is enabled to provide Extended Message Data. - If clear, the function is not enabled to provide Extended Message Data.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO 26260x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2268Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGMSI_CAP_OFF_04H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr22970x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_04H_REGMessage Address Register for MSI (Offset 04h).falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2280Reserved for future use.100x0RPCI_MSI_CAP_OFF_04HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2296Message Address - System-specified message address.If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set, the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI transaction. Address[1:0] are set to 00b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3120x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGMSI_CAP_OFF_08H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr23760x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_08H_REGFor a function that supports a 32-bit message address, - bits[31:16] of this register represent the Extended Message Data, and - bits[15:0] of this register represent the Message DataFor a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.falsefalsefalsefalsePCI_MSI_CAP_OFF_08HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2347For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.For a function that supports a 64-bit message address, it contains lower 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0AHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2375For a function that supports a 32-bit message address, this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is outside the MSI Capability structure and undefined. For the MSI Capability structures with Per-vector Masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is RsvdP. If the Extended Message Data Enable bit (bit 26 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the DWORD Memory Write transaction uses Extended Message Data for the upper 16 bits; otherwise, it uses 0000h for the upper 16 bits.For a function that supports a 64-bit message address, it contains upper 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGMSI_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr24400xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REGFor a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains Message Data.falsefalsefalsefalsePCI_MSI_CAP_OFF_0CHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2419For a function that supports a 32-bit message address, this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0EHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2439For a function that supports a 32-bit message address, this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGMSI_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr24690x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_10H_REGFor a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_10HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2468Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit, contains Mask Bits.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGMSI_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr24850x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_14H_REGPending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_14HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2484Pending Bits. For each pending bit that is set, the function has a pending associated message.3100x00000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAPPF0_PCIE_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr58500x70R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAPPF PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUSregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr26430x0R0x0002b010PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCI Express Capabilities, ID, Next Pointer Register.falsefalsefalsefalsePCIE_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2504Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure.700x10RPCIE_CAP_NEXT_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2519Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580xb0RPCIE_CAP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2543Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number.A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example, through a new Capability field) is permitted to increment this field. All such changes to the PCI Express Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as functions reporting any such Capability Version numbers will contain a PCI Express Capability structure that is compatible with that piece of software.The controller hardwires this field to 2h for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.Note: This register field is sticky.19160x2RPCIE_DEV_PORT_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2570Device/Port Type. Indicates the specific type of this PCI Express function.Note: Different functions in a Multi-Function Device can generally be of different types.Defined encodings for functions that implement a Type 00h PCI Configuration Space header are: - 0000b PCI Express Endpoint - 0001b Legacy PCI Express EndpointDefined encodings for functions that implement a Type 01h PCI Configuration Space header are: - 0100b Root Port of PCI Express Root Complex - 0101b Upstream Port of PCI Express Switch - 0110b Downstream Port of PCI Express SwitchAll other encodings are Reserved.Note: Different Endpoint types have notably different requirements in Section 1.3.2 of PCI Express Base Specification regarding I/O resources, Extended Configuration Space, and other capabilities.2320RPCIE_SLOT_IMPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2586Slot Implemented. When set, this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit is undefined for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 24240x0RPCIE_INT_MSG_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2628PCIE Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Base Specification.Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this Capability structure.For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register.For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant.If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.29250x00RRSVDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2635Reserved.30300x0RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2642Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGDEVICE_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr27910x4R0x00008021PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REGDevice Capabilities Register.The Device Capabilities register identifies PCI Express device function specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_PAYLOAD_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2675Max_Payload_Size Supported.This field indicates the maximum payload size that the function can support for TLPs.Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedThe functions of a Multi-Function Device are permitted to report different values for this field.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x1RPCIE_CAP_PHANTOM_FUNC_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2729Phantom Functions Supported.This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the Tag identifier (see Section 2.2.6.2 of PCI Express Base Specification for a description of Tag Extensions).With every Function in an ARI Device, the Phantom Functions Supported field must be set to 00b. The remainder of this field description applies only to non-ARI Multi-Function Devices.This field indicates the number of most significant bits of the Function Number portion of Requester ID that are logically combined with the Tag identifier.Defined encodings are: - 00b: No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. - 01b: The most significant bit of the Function number in Requester ID is used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. - 10b: The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as Phantom Functions. - 11b: All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single Function 0 that is permitted to use all other Function Numbers as Phantom Functions.Note: Phantom Function support for the function must be enabled by the Phantom Functions Enable field in the Device Control register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.430x0RPCIE_CAP_EXT_TAG_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2756Extended Tag Field Supported.This bit, in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register, indicates the maximum supported size of the Tag field as a Requester. This bit must be set if the 10-Bit Tag Requester Supported bit is set.Defined encodings are: - 0b: 5-bit Tag field supported - 1b: 8-bit Tag field supportedNote: 8-bit Tag field generation must be enabled by the Extended Tag Field Enable bit in the Device Control register of the Requester Function before 8-bit Tags can be generated by the Requester. See Section 2.2.6.2 of PCI Express Base Specificationfor interactions with enabling the use of 10-Bit Tags.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.550x1RRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2763Reserved for future use.1460x000RPCIE_CAP_ROLE_BASED_ERR_REPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2783Role-Based Error Reporting. When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.15150x1RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2790Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSDEVICE_CONTROL_DEVICE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr31360x8R/W0x00002010PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUSDevice Control and Device Status Register.This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters.falsefalsefalsefalsePCIE_CAP_CORR_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2814Correctable Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_COR Messages (for more details, see section 6.2.5, section 6.2.6, and section 6.2.10.2 of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR Message is generated.000x0R/WPCIE_CAP_NON_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2831Non-Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages (for more details, see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each function from point-of-view of the respective Function.For a Root Port, the reporting of Non-fatal errors is internal to the root. No external ERR_NONFATAL Message is generated.110x0R/WPCIE_CAP_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2847Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_FATAL Messages (for more details, see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of Fatal errors is internal to the root. No external ERR_FATAL Message is generated.220x0R/WPCIE_CAP_UNSUPPORT_REQ_REP_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2861Unsupported Request Reporting Enable.This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (for more details, see section 6.2.5 and section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each Function from point-of-view of the respective Function.330x0R/WPCIE_CAP_EN_REL_ORDERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2881Enable Relaxed Ordering.If this bit is set, the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details, see section 2.2.6.4 and section 2.4 of PCI Express Base Specification).For a function that never sets the Relaxed Ordering attribute in transactions it initiates as a Requester, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x1R/WPCIE_CAP_MAX_PAYLOAD_SIZE_CSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2918Max_Payload_Size.This field sets maximum TLP payload size for the Function. As a Receiver, the Function must handle TLPs as large as the set value. As a Transmitter, the Function must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities (DEVICE_CAPABILITIES_REG) register (for more details, see section 7.5.3.3 of PCI Express Base Specification).Defined encodings for this field are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedFor Functions that support only the 128-byte max payload size, the controller hardwires this field to 000b.System software is not required to program the same value for this field for all the Functions of a Multi-Function device (for more details, see section 2.2.2 of PCI Express Base Specification).For ARI Devices, Max_Payload_Size is determined solely by the setting in Function0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.750x0R/WPCIE_CAP_EXT_TAG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2950Extended Tag Field Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If the Extended Tag Field Enable bit is set, the function is permitted to use an 8-bit Tag field as a Requester - If the Extended Tag Field Enable bit is clear, the Function is restricted to a 5-bit Tag fieldSee section 2.2.6.2 of PCI Express Base Specification for required behavior when the 10-Bit Tag Requester Enable bit is set.If software changes the value of the Extended Tag Field Enable bit while the function has outstanding Non-Posted Requests, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO 88R/WPCIE_CAP_PHANTOM_FUNC_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr2984Phantom Functions Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If this bit is set, it enables a function to use unclaimed functions as Phantom functions to extend the number of outstanding transaction identifiers - If this bit is clear, the function is not allowed to use Phantom functionsFor more details, see section 2.2.6.2 of PCI Express Base Specification.Software should not change the value of this bit while the function has outstanding Non-Posted Requests; otherwise, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO 99RPCIE_CAP_AUX_POWER_PM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3011Aux Power PM Enable.This bit is derived by sampling the sys_aux_pwr_det input.When set this bit, enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems should continue to indicate PME Aux power requirements. Aux power is allocated as requested in the Aux_Current field of the Power Management Capabilities register (PMC), independent of the PME_En bit in the Power Management Control/Status register (PMCSR). For Multi-Function devices, a component is allowed to draw Aux power if at least one of the functions has this bit set.Note: Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this bit is not modified by Conventional Reset.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: This register field is sticky.1010R/WPCIE_CAP_EN_NO_SNOOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3038Enable No Snoop.If this bit is set, the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express Base Specification).Note: Setting this bit to 1b should not cause a function to set the No Snoop attribute on all transactions that it initiates. Even when this bit is set, a function is only permitted to set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system.The controller hardwires this bit 0b if a function would never set the No Snoop attribute in transactions it initiates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 11110x0RPCIE_CAP_MAX_READ_REQ_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3061Max_Read_Request_Size.This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: - 000b: 128 bytes maximum Read Request size - 001b: 256 bytes maximum Read Request size - 010b: 512 bytes maximum Read Request size - 011b: 1024 bytes maximum Read Request size - 100b: 2048 bytes maximum Read Request size - 101b: 4096 bytes maximum Read Request size - 110b: Reserved - 111b: ReservedFor functions that do not generate Read Requests larger than 128 bytes and functions that do not generate Read Requests on their own behalf, the controller implements this field as Read Only (RO) with a value of 000b.14120x2R/W--16150x0rPCIE_CAP_NON_FATAL_ERR_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3079Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.17170x0R/W1C--18180x0rPCIE_CAP_UNSUPPORTED_REQ_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3094Unsupported Request Detected.This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function Device, each function indicates status of errors as perceived by the respective function.19190x0R/W1CPCIE_CAP_AUX_POWER_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3107AUX Power Detected.Functions that require Aux power report this bit as set if Aux power is detected by the function.This bit is derived by sampling the sys_aux_pwr_det input.2020RPCIE_CAP_TRANS_PENDINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3127Transactions Pending.Endpoints:When set, this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.Root and Switch Ports:The controller hardwires this bit to 0b.21210x0RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3135Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGLINK_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr34910xCR0x00780c84PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES_REGLink Capabilities Register.The Link Capabilities register identifies PCI Express Link specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3176Max Link Speed.This field indicates the maximum Link speed of the associated Port.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are reserved.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x4RPCIE_CAP_MAX_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3212Maximum Link Width.This field indicates the maximum Link width (xN – corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width.Defined encodings are: - 00 0001b x1 - 00 0010b x2 - 00 0100b x4 - 00 1000b x8 - 00 1100b x12 - 01 0000b x16 - 10 0000b x32All other encodings are Reserved.Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.For a description of this standard PCIe register field, see the PCI Express Base Specification.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.940x08RPCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3237Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification.Defined encodings are: - 00b: No ASPM Support - 01b: L0s Supported - 10b: L1 Supported - 11b: L0s and L1 SupportedMulti-Function devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.11100x3RPCIE_CAP_L0S_EXIT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3295L0s Exit Latency.This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; however, see the Implementation Note "Potential Issues With Legacy Software When L0s is Not Supported" in section 5.4.1.1 of PCI Express Base Specification for the recommended value.Defined encodings are: - 000b: Less than 64 ns - 001b: 64 ns to less than 128 ns - 010b: 128 ns to less than 256 ns - 011b: 256 ns to less than 512 ns - 100b: 512 ns to less than 1 us - 101b: 1 us to less than 2 us - 110b: 2 us to 4 us - 111b: More than 4 usNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1412RPCIE_CAP_L1_EXIT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3349L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined.Defined encodings are: - 000b: Less than 1us - 001b: 1 us to less than 2 us - 010b: 2 us to less than 4 us - 011b: 4 us to less than 8 us - 100b: 8 us to less than 16 us - 101b: 16 us to less than 32 us - 110b: 32 us to 64 us - 111b: More than 64 μsNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1715RPCIE_CAP_CLOCK_POWER_MANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3383Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.For Downstream Ports, the controller hardwires this bit to 0b.Note: This register field is sticky.1818RPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3403Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19190x1RPCIE_CAP_DLL_ACTIVE_REP_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3422Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.20200x1RPCIE_CAP_LINK_BW_NOT_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3448Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x1RPCIE_CAP_ASPM_OPT_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3467ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 22220x1RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3474Reserved for future use.23230x0RPCIE_CAP_PORT_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3490Port Number. This field indicates the PCI Express Port number for the given PCI Express Link.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGLINK_CONTROL_LINK_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr40320x10R/W0x10000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REGLink Control and Link Status Register.This register controls and provides information about PCI Express Link specific parameters.falsefalsefalsefalsePCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3541Active State Power Management (ASPM) Control.This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to enable ASPM.Defined encodings are: - 00b: Disabled - 01b: L0s Entry Enabled - 10b: L1 Entry Enabled - 11b: L0s and L1 Entry EnabledNote: "L0s Entry Enabled" enables the Transmitter to enter L0s. If L0s is supported, the Receiver must be capable of entering L0s even when the Transmitter is disabled from entering L0s (00b or 10b).ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link. When disabling ASPM L1, software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link. ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1.For Multi-Function Devices (including ARI Devices), it is recommended that software program the same value for this field in all Functions. For non-ARI Multi-Function Devices, only capabilities enabled in all Functions are enabled for the component as a whole.For ARI Devices, ASPM Control is determined solely by the setting in Function0, regardless of Function 0's D-state. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise, the result is undefined.100x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3549Reserved for future use.220x0RPCIE_CAP_RCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3591Read Completion Boundary (RCB).Root Ports:Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b: 64 byte - 1b: 128 byteThe controller hardwires this bit for a Root Port and returns its RCB support capabilities.Endpoints and Bridges:Optionally set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Refer to Section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b 64 byte - 1b 128 byteConfiguration software must only set this bit if the Root Port Upstream from the Endpoint or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion Boundary bit).For functions that do not implement this feature, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 330x0RPCIE_CAP_LINK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3619Link Disable.This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.After clearing this bit, software must honor timing requirements defined in Section 6.6.1 with respect to the first Configuration Read following a Conventional Reset.In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO 44R/WPCIE_CAP_RETRAIN_LINKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3650Retrain Link.A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. If the Port is in DPC when a write of 1b to this bit occurs, the result is undefined. Reads of this bit always return 0b.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.This bit is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.This bit always returns 0b when read.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description 55R/WPCIE_CAP_COMMON_CLK_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3685Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.For non-ARI Multi-Function Devices, software must program the same value for this bit in all Functions. If not all Functions are Set, then the component must as a whole assume that its reference clock is not common with the Upstream component.For ARI Devices, Common Clock Configuration is determined solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies.After changing the value in this bit in both components on a Link, software must trigger the Link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port.660x0R/WPCIE_CAP_EXTENDED_SYNCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3704Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI Express Base Specification). This mode provides external devices (for example, logic analyzers) monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication.For Multi-Function devices if any function has this bit set, then the component must transmit the additional Ordered Sets when exiting L0s or when in Recovery.770x0R/WPCIE_CAP_EN_CLK_POWER_MANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3748Enable Clock Power Management.Applicable only for Upstream Ports and with form factors that support a "Clock Request" (CLKREQ#) mechanism, this bit operates as follows: - 0b: Clock power management is disabled and device must hold CLKREQ# signal low. - 1b: When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according to protocol defined in appropriate form factor specification.For a non-ARI Multi-Function Device, power-management-configuration software must only Set this bit if all Functions of the Multi-Function Device indicate a 1b in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage Link clock only if this bit is Set for all Functions.For ARI Devices, Clock Power Management is enabled solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.The CLKREQ# signal may also be controlled via the L1 PM Substates mechanism. Such control is not affected by the setting of this bit.For Downstream Ports and components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities register), the controller hardwires this bit to 0b.The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This register field is sticky.88R/WPCIE_CAP_HW_AUTO_WIDTH_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3771Hardware Autonomous Width Disable.When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.For components that do not implement the ability autonomously to change Link width, the ciontroller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WPCIE_CAP_LINK_BW_MAN_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3795Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1010R/WPCIE_CAP_LINK_AUTO_BW_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3819Link Autonomous Bandwidth Management Interrupt Enable.When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1111R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3827Reserved for future use.13120x0RPCIE_CAP_DRS_SIGNALING_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3866DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b: DRS not ReportedIf DRS Supported is set, receiving a DRS Message will set DRS Message Received in the Link Status 2 Register but will otherwise have no effect - 01b: DRS Interrupt EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, and either MSI or MSI-X is enabled, an MSI or MSI-X interrupt is generated using the vector in Interrupt Message Number (section 7.5.3.2) - 10b: DRS to FRS Signaling EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, the Port must send an FRS Message Upstream with the FRS Reason field set to DRS Message Received.Behavior is undefined if this field is set to 10b and the FRS Supported bit in the Device Capabilities 2 Register is Clear.Behavior is undefined if this field is set to 11b.For Downstream Ports with the DRS Supported bit clear in the Link Capabilities 2 register, the controller hardwires this field to 00b.This field is Reserved for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES2_REG.DRS_SUPPORTED ? RW : RO 15140x0R/WPCIE_CAP_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3891Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.The value in this field is undefined when the Link is not up.1916RPCIE_CAP_NEGO_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3911Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link.Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32All other encodings are Reserved. The value in this field is undefined when the Link is not up.2520RRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3919Reserved for future use.26260x0RPCIE_CAP_LINK_TRAININGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3936Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and the controller hardwires it to 0b.2727RPCIE_CAP_SLOT_CLK_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3956Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear.For a Multi-Function Device, each Function must report the same value for this bit.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 28280x1RPCIE_CAP_DLL_ACTIVEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr3972Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.This bit must be implemented if the Data Link Layer Link Active Reporting Capable bit is 1b. Otherwise, the controller hardwires it to 0b.2929RPCIE_CAP_LINK_BW_MAN_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4005Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of 1b to the Retrain Link bit.Note: This bit is set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason. - Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.The default value of this bit is 0b.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.3030R/W1CPCIE_CAP_LINK_AUTO_BW_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4031Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.3131R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REGSLOT_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr42470x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_SLOT_CAPABILITIES_REGSlot Capabilities Register.The Slot Capabilities register identifies PCI Express slot specific capabilities.falsefalsefalsefalsePCIE_CAP_ATTENTION_INDICATOR_BUTTONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4052Attention Button Present. When set, this bit indicates that an Attention Button for this slot is electrically controlled by the chassis.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 000x0RPCIE_CAP_POWER_CONTROLLERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4067Power Controller Present. When set, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 110x0RPCIE_CAP_MRL_SENSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4080MRL Sensor Present. When set, this bit indicates that an MRL Sensor is implemented on the chassis for this slot.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 220x0RPCIE_CAP_ATTENTION_INDICATORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4094Attention Indicator Present. When set, this bit indicates that an Attention Indicator is electrically controlled by the chassis.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 330x0RPCIE_CAP_POWER_INDICATORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4108Power Indicator Present. When set, this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 440x0RPCIE_CAP_HOT_PLUG_SURPRISEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4125Hot-Plug Surprise. When set, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow for such removal without impacting continued software operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 550x0RPCIE_CAP_HOT_PLUG_CAPABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4138Hot-Plug Capable. When set, this bit indicates that this slot is capable of supporting hot-plug operations.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 660x0RPCIE_CAP_SLOT_POWER_LIMIT_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4170Slot Power Limit Value. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot (for more detais, see Section 6.9 of PCI Express Base Specification) or by other means to the adapter.Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field except when the Slot Power Limit Scale field equals 00b (1.0x) and Slot Power Limit Value exceeds EFh, the following alternative encodings are used: - F0h: 250 W Slot Power Limit - F1h: 275 W Slot Power Limit - F2h: 300 W Slot Power Limit - F3h - FFh: Reserved for Slot Power Limit values above 300 WThis register must be implemented if the Slot Implemented bit is set.Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message.The default value prior to hardware/firmware initialization is 0000 0000b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 1470x00RPCIE_CAP_SLOT_POWER_LIMIT_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4195Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details, see Section 6.9 of PCI Express Base Specification).Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001xThis register must be implemented if the Slot Implemented bit is set.Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message.The default value prior to hardware/firmware initialization is 00b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 16150x0RPCIE_CAP_ELECTROMECH_INTERLOCKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4209Electromechanical Interlock Present. When set, this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 17170x0RPCIE_CAP_NO_CMD_CPL_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4227No Command Completed Support. When set, this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the hot-plug capable Port is able to accept writes to all fields of the Slot Control register without delay between successive writes.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 18180x0RPCIE_CAP_PHY_SLOT_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4246Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis, regardless of the form factor associated with the slot. This field must be initialized to zero for Ports connected to devices that are either integrated on the system board or integrated within the same silicon as the Switch device or Root Port.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31190x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUSSLOT_CONTROL_SLOT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr45930x18R/W0x000003c0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUSSlot Control and Status Register.This register controls and provides information about PCI Express Slot specific parameters.falsefalsefalsefalsePCIE_CAP_ATTENTION_BUTTON_PRESSED_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4265Attention Button Pressed Enable. When set to 1b, this bit enables software notification on an attention button pressed event (for more details, see Section 6.7.3 of PCI Express Base Specification).If the Attention Button Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b.000x0R/WPCIE_CAP_POWER_FAULT_DETECTED_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4278Power Fault Detected Enable. When set, this bit enables software notification on a power fault event (for more details, see Section 6.7.3 of PCI Express Base Specification).If a Power Controller that supports power fault detection is not implemented, this bit is permitted to be read-only with a value of 0b.110x0R/WPCIE_CAP_MRL_SENSOR_CHANGED_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4291MRL Sensor Changed Enable. When set, this bit enables software notification on a MRL sensor changed event (for more details, see Section 6.7.3 of PCI Express Base Specification).If the MRL Sensor Present bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b.220x0R/WPCIE_CAP_PRESENCE_DETECT_CHANGE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4304Presence Detect Changed Enable. When set, this bit enables software notification on a presence detect changed event (for more details, see Section 6.7.3 of PCI Express Base Specification).If the Hot-Plug Capable bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b.330x0R/WPCIE_CAP_CMD_CPL_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4325Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b), when set, this bit enables software notification when a hot-plug command is completed by the Hot-Plug Controller.If Command Completed notification is not supported, the controller hardwires this bit must to 0b.Write value is gated with PCIE_CAP_NO_CMD_CPL_SUPPORT field in SLOT_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: SLOT_CAPABILITIES_REG.PCIE_CAP_NO_CMD_CPL_SUPPORT ? RO : RW 44R/WPCIE_CAP_HOT_PLUG_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4336Hot-Plug Interrupt Enable. When set, this bit enables generation of an interrupt on enabled hot-plug events.If the Hot Plug Capable bit in the Slot Capabilities register is clear, this bit is permitted to be read-only with a value of 0b.550x0R/WPCIE_CAP_ATTENTION_INDICATOR_CTRLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4359Attention Indicator Control. If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting, if required to, for the previous command to complete in which case the read value is undefined.Defined encodings are: - 00b Reserved - 01b On - 10b Blink - 11b OffNote: The default value of this field must be one of the non-Reserved values. If the Attention Indicator Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 00b.760x3R/WPCIE_CAP_POWER_INDICATOR_CTRLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4382Power Indicator Control. If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting, if required to, for the previous command to complete in which case the read value is undefined.Defined encodings are: - 00b: Reserved - 01b: On - 10b: Blink - 11b: OffNote: The default value of this field must be one of the non-Reserved values. If the Power Indicator Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 00b.980x3R/WPCIE_CAP_POWER_CONTROLLER_CTRLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4407Power Controller Control. If a Power Controller is implemented, this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write, if required to, without waiting for the previous command to complete in which case the read value is undefined.Note: In some cases the power controller may autonomously remove slot power or not respond to a power-up request based on a detected fault condition, independent of the Power Controller Control setting.The defined encodings are: - 0b: Power On - 1b: Power OffIf the Power Controller Present bit in the Slot Capabilities register is clear, then writes to this bit have no effect and the read value of this bit is undefined.10100x0R/WPCIE_CAP_ELECTROMECH_INTERLOCK_CTRLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4419Electromechanical Interlock Control. If an Electromechanical Interlock is implemented, a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit always returns a 0b.11110x0R/WPCIE_CAP_DLL_STATE_CHANGED_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4433Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b, this bit enables software notification when Data Link Layer Link Active bit is changed.If the Data Link Layer Link Active Reporting Capable bit is 0b, this bit is permitted to be read-only with a value of 0b.12120x0R/W--13130x0rRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4441Reserved for future use.15140x0RPCIE_CAP_ATTENTION_BUTTON_PRESSEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4452Attention Button Pressed. If an Attention Button is implemented, this bit is set when the attention button is pressed. If an Attention Button is not supported, this bit must not be set.16160x0R/W1CPCIE_CAP_POWER_FAULT_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4469Power Fault Detected.If a Power Controller that supports power fault detection is implemented, this bit issSet when the Power Controller detects a power fault at this slot.Note: Depending on hardware capability, it is possible that a power fault can be detected at any time, independent of the Power Controller Control setting or the occupancy of the slot. If power fault detection is not supported, this bit must not be set.17170x0R/W1CPCIE_CAP_MRL_SENSOR_CHANGEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4480MRL Sensor Changed.If an MRL sensor is implemented, this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be set.18180x0R/W1CPCIE_CAP_PRESENCE_DETECTED_CHANGEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4490Presence Detect Changed.This bit is set when the value reported in the Presence Detect State bit is changed.19190x0R/W1CPCIE_CAP_CMD_CPLDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4511Command Completed.If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b), this bit is set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command. The Command Completed status bit is set as an indication to host software that the Hot-Plug Controller has processed the previous command and is ready to receive the next command; it provides no guarantee that the action corresponding to the command is complete.If Command Completed notification is not supported, the controller hardwires this bit to 0b.20200x0R/W1CPCIE_CAP_MRL_SENSOR_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4524MRL Sensor State.This bit reports the status of the MRL sensor if implemented.Defined encodings are: - 0b: MRL Closed - 1b: MRL Open21210x0RPCIE_CAP_PRESENCE_DETECT_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4555Presence Detect State.This bit indicates the presence of an adapter in the slot, reflected by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. Note that the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. Consequently, form factors that require a power controller for hot-plug must implement a physical pin presence detect mechanism.Defined encodings are: -0b: Slot Empty -1b: Adapter Present in slotThis bit must be implemented on all Downstream Ports that implement slots. For Downstream Ports not connected to slots (where the Slot Implemented bit of the PCI Express Capabilities register is 0b), the controller hardwires this bit to 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 2222RPCIE_CAP_ELECTROMECH_INTERLOCK_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4568Electromechanical Interlock Status.If an Electromechanical Interlock is implemented, this bit indicates the status of the Electromechanical Interlock.Defined encodings are: - 0b: Electromechanical Interlock Disengaged - 1b: Electromechanical Interlock Engaged23230x0RPCIE_CAP_DLL_STATE_CHANGEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4584Data Link Layer State Changed.This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed.In response to a Data Link Layer State Changed event, software must read the Data Link Layer Link Active bit of the Link Status register to determine if the Link is active before initiating configuration cycles to the hot plugged device.24240x0R/W1CRSVDP_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4592Reserved for future use.31250x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REGROOT_CONTROL_ROOT_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr47050x1CR/W0x00010000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REGRoot Control and Capabilities Register.This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities.falsefalsefalsefalsePCIE_CAP_SYS_ERR_ON_CORR_ERR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4611System Error on Correctable Error Enable. If set, this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific.000x0R/WPCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4623System Error on Non-Fatal Error Enable. If set, this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific.110x0R/WPCIE_CAP_SYS_ERR_ON_FATAL_ERR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4635System Error on Fatal Error Enable. If set, this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific.220x0R/WPCIE_CAP_PME_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4647PME Interrupt Enable. When set, this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details, see Table 7-29 of PCI Express Base Specification). A PME interrupt is also generated if the PME Status bit is set when this bit is changed from clear to set.330x0R/WPCIE_CAP_CRS_SW_VISIBILITY_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4666CRS Software Visibility Enable. When set, this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details, see section 2.3.1 of PCI Express Base Specification).For Root Ports that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: ROOT_CONTROL_ROOT_CAPABILITIES_REG.PCIE_CAP_CRS_SW_VISIBILITY ? RW : RO 440x0R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4674Reserved for future use.1550x000RPCIE_CAP_CRS_SW_VISIBILITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4696CRS Software Visibility Capable.For a description of this standard PCIe register field, see the PCI Express Base Specification.CRS Software Visibility. When set, this bit indicates that the Root Port is capable of returning Configuration Request Retry Status (CRS) Completion Status to software (for more details, see section 2.3.1 of PCI Express Base Specification).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R (Sticky) Note: This register field is sticky.16160x1RRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4704Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REGROOT_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr47540x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_ROOT_STATUS_REGRoot Status Register.The Root Status register provides information about PCI Express device specific parameters.falsefalsefalsefalsePCIE_CAP_PME_REQ_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4720PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set.1500x0000RPCIE_CAP_PME_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4731PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b.16160x0R/W1CPCIE_CAP_PME_PENDINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4745PME Pending. This bit indicates that another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME Requester ID field appropriately. The PME Pending bit is cleared by hardware if no more PMEs are pending.17170x0RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4753Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGDEVICE_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr50160x24R0x80011c1fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REGDevice Capabilities 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4793Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value.This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and must be hardwired to 0000b.Four time value ranges are defined: - Range A: 50 us to 10 ms - Range B: 10 ms to 250 ms - Range C: 250 ms to 4 s - Range D: 4 s to 64 sBits are set according to the list below to show timeout value ranges supported. - 0000b Completion Timeout programming not supported – the Function must implement a timeout value in the range 50 μs to 50 ms. - 0001b Range A - 0010b Range B - 0011b Ranges A and B - 0110b Ranges B and C - 0111b Ranges A, B, and C - 1110b Ranges B, C, and D - 1111b Ranges A, B, C, and DAll other values are Reserved.It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.300xfRPCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4811Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism.The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.This mechanism is optional for Root Ports.For all other Functions this field is Reserved and the controller hardwires this bit to 0b.440x1RPCIE_CAP_ARI_FORWARD_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4823ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. For more details, see section 6.13 of PCI Express Base Specification.550x0RPCIE_CAP_ATOMIC_ROUTING_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4835AtomicOp Routing Supported. Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.660x0RPCIE_CAP_32_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr484832-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.770x0RPCIE_CAP_64_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr486164-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.880x0RPCIE_CAP_128_CAS_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4872128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.990x0RPCIE_CAP_NO_RO_EN_PR2PR_PARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4890No RO-enabled PR-PR Passing. If this bit is set, the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute field being Set.This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit.For all other functions, this bit must be 0b.10100x1RPCIE_CAP_LTR_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4913LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism.Root Ports, Switches and Endpoints are permitted to implement this capability.For a Multi-Function Device associated with an Upstream Port, each Function must report the same value for this bit.For Bridges and other Functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.11110x1RPCIE_CAP_TPH_CMPLT_SUPPORT_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4932TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions, this field is Reserved.Defined Encodings are: - 00b: TPH and Extended TPH Completer not supported. - 01b: TPH Completer supported; Extended TPH Completer not supported. - 10b: Reserved. - 11b: Both TPH and Extended TPH Completer supported.For more details, see section 6.17 of PCI Express Base Specification.12120x1RPCIE_CAP_TPH_CMPLT_SUPPORT_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4939TPH Completer Supported Bit 1.13130x0RPCIE_CAP2_LN_SYS_CLSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4960LN System CLS. Applicable only to Root Ports and RCRBs; must be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect.Encodings are: - 00b LN Completer either not supported or not in effect - 01b LN Completer with 64-byte cachelines in effect - 10b LN Completer with 128-byte cachelines in effect - 11b ReservedNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 15140x0RPCIE_CAP2_10_BIT_TAG_COMP_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr497010-Bit Tag Completer Supported. If this bit is set, the Function supports 10-Bit Tag Completer capability; otherwise, the Function does not. For more details, see section 2.2.6.2. of PCI Express Base Specification.16160x1RPCIE_CAP2_10_BIT_TAG_REQ_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr498810-Bit Tag Requester Supported. If this bit is set, the Function supports 10-Bit Tag Requester capability; otherwise, the Function does not.This bit must not be set if the 10-Bit Tag Completer Supported bit is clear.Note: 10-Bit Tag field generation must be enabled by the 10-Bit Tag Requester Enable bit in the Device Control 2 register of the Requester Function before 10-Bit Tags can be generated by the Requester. For more details, see section 2.2.6.2. of PCI Express Base Specification.17170x0R--23180x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr4995Reserved for future use.30240x00RPCIE_CAP_FRS_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5015FRS Supported. When set, indicates support for the optional Function Readiness Status (FRS) capability.Must be set for all Functions that support generation or reception capabilities of FRS Messages.Must not be set by Switch Functions that do not generate FRS Messages on their own behalf.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGDEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr51470x28R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REGDevice Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5074Completion Timeout Value. In device Functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and controller hardwires it to 0000b.A Function that does not support this optional capability must hardwire this field to 0000b and is required to implement a timeout value in the range 50 μs to 50 ms. Functions that support Completion Timeout programmability must support the values given below corresponding to the programmability ranges indicated in the Completion Timeout Ranges Supported field.Defined encodings: - 0000b Default range: 50 μs to 50 msIt is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.Values available if Range A (50 μs to 10 ms) programmability range is supported: - 0001b: 50 μs to 100 μs - 0010b: 1 ms to 10 msValues available if Range B (10 ms to 250 ms) programmability range is supported: - 0101b 16 ms to 55 ms - 0110b 65 ms to 210 msValues available if Range C (250 ms to 4 s) programmability range is supported: - 1001b 260 ms to 900 ms - 1010b 1 s to 3.5 sValues available if the Range D (4 s to 64 s) programmability range is supported: - 1101b 4 s to 13 s - 1110b 17 s to 64 sValues not defined above are Reserved.Software is permitted to change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding Requests, and is permitted to base the start time for each Request either on when this value was changed or on when each request was issued.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300x0R/WPCIE_CAP_CPL_TIMEOUT_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5095Completion Timeout Disable. When set, this bit disables the Completion Timeout mechanism.This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this optional capability are permitted to hardwire this bit to 0bSoftware is permitted to set or clear this bit at any time. When set, the Completion Timeout detection mechanism is disabled. If there are outstanding Requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding Requests. If this is done, it is permitted to base the start time for each Request on either the time this bit was cleared or the time each Request was issued.440x0R/WPCIE_CAP_ARI_FORWARD_SUPPORT_CSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5113ARI Forwarding Enable. When set, the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. For more details, see Section 6.13 of PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 550x0R--960x0rPCIE_CAP_LTR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5146LTR Mechanism Enable. When set to 1b, this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages.For a Multi-Function Device associated with an Upstream Port of a device that implements LTR, the bit in Function 0 is RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is RsvdP.Functions that do not implement the LTR mechanism are permitted to hardwire this bit to 0b.For Downstream Ports, this bit must be reset to the default value if the Port goes to DL_Down status.The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.Note: RW for function #0 and RsdvP for all other functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R 1010R/W--31110x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGLINK_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr53130x2CR/W0x81800000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES2_REGLink Capabilities 2 Register.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5158Reserved for future use.000x0RPCIE_CAP_SUPPORT_LINK_SPEED_VECTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5189Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. For more details, see section 8.2.1 of PCI Express Base Specification.Bit definitions within this field are: - Bit 0 2.5 GT/s - Bit 1 5.0 GT/s - Bit 2 8.0 GT/s - Bit 3 16.0 GT/s - Bit 4 32.0 GT/s - Bits 6:5 RsvdPMulti-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.71RPCIE_CAP_CROSS_LINK_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5218Crosslink Supported. When set to 1b, this bit indicates that the associated Port supports crosslinks (for more details, see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link speeds of 8.0 GT/s or higher, this bit indicates that the associated Port does not support crosslinks. When set to 0b on a Port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, this bit provides no information regarding the Port’s level of crosslink support.It is recommended that this bit be Set in any Port that supports crosslinks even though doing so is only required for Ports that also support operating at 8.0 GT/s or higher Link speeds.Note: Software should use this bit when referencing fields whose definition depends on whether or not the Port supports crosslinks (for more details, see section 7.7.3.4 of PCI Express Base Specification).Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.880x0RRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5226Reserved for future use.2290x0000RPCIE_CAP_RETIMER_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5252Retimer Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 23230x1RPCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5278Two Retimers Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds if the Retimer Presence Detect Supported bit is also set to 1b.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 24240x1R/WRSVDP_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5286Reserved for future use.30250x00RDRS_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5312DRS Supported. When set, indicates support for the optional Device Readiness Status (DRS) capability.Must be Set in Downstream Ports that support DRS.Must be Set in Downstream Ports that support FRS.For Upstream Ports that support DRS, it is strongly recommended that this bit be Set in Function 0. For all other Functions associated with an Upstream Port, this bit must be Clear.127Must be Clear in Functions that are not associated with a Port.RsvdP in all other Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGLINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr58490x30R/W0x00010000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REGLink Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_TARGET_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5377Target Link Speed. For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired target Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.If a value is written to this field that does not correspond to a supported speed (as indicated by the Supported Link Speeds Vector), the result is undefined.If either of the Enter Compliance or Enter Modified Compliance bits are implemented, then this field must also be implemented.The default value of this field is the highest Link speed supported by the component (as reported in the Max Link Speed field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode.For Upstream Ports, if the Enter Compliance bit is Clear, this field is permitted to have no effect.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a description of this standard PCIe register field, see the PCI Express Base Specification. In M-PCIe mode, the contents of this field are derived from other registers.Note: This register field is sticky.30R/WPCIE_CAP_ENTER_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5410Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link.Default value of this bit following Fundamental Reset is 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: This register field is sticky.440x0R/WPCIE_CAP_HW_AUTO_SPEED_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5435Hardware Autonomous Speed Disable. When set, this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.550x0R/WPCIE_CAP_SEL_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5465Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. For more details, see section 4.2.6 of PCI Express Base Specification.Encodings: - 1b: -3.5 dB - 0b: -6 dBWhen the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RPCIE_CAP_TX_MARGINPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5499Transmit Margin – This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base Specification for details of how the Transmitter voltage level is determined in various states).Encodings: - 000b: Normal operating range - 001b-111b: As defined in Section 8.3.4 not all encodings are required to be implemented.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 000b.This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: This register field is sticky.970x0R/WPCIE_CAP_ENTER_MODIFIED_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5526Enter Modified Compliance. When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.10100x0R/WPCIE_CAP_COMPLIANCE_SOSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5553Compliance SOS. When set to 1b, the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.11110x0R/WPCIE_CAP_COMPLIANCE_PRESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5595Compliance Preset/De-emphasis.For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in section 4.2.3.2 of PCI Express Base Specification . Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way.For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.Defined Encodings are: - 0001b: -3.5 dB - 0000b: -6 dBWhen the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.15120x0R/WPCIE_CAP_CURR_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5621Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed, this bit reflects the level of de-emphasis.Encodings: - 1b: -3.5 dB - 0b: -6 dBThe value in this bit is undefined when the Link is not operating at 5.0 GT/s speed.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For components that support speeds greater than 2.5 GT/s, Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions of the Port. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE.16160x1RPCIE_CAP_EQ_CPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5643Equalization 8.0 GT/s Complete. When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.17170x0RPCIE_CAP_EQ_CPL_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5665Equalization 8.0 GT/s Phase 1 Successful. When set to 1b, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.18180x0RPCIE_CAP_EQ_CPL_P2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5687Equalization 8.0 GT/s Phase 2 Successful. When set to 1b, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_EQ_CPL_P3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5709EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.20200x0RPCIE_CAP_LINK_EQ_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5727Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details, see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.21210x0R/W1CPCIE_CAP_RETIMER_PRE_DETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5753Retimer Presence Detected. When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Retimer Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.For Ports that have the Retimer Presence Detect Supported bit set to 0b, the controller hardwires this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and is RsvdZ in all other Functions.Note: This register field is sticky.22220x0RPCIE_CAP_TWO_RETIMERS_PRE_DETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5779Two Retimers Presence Detected. When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and RsvdZ in all other Functions.Note: This register field is sticky.23230x0R--25240x0rRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5787Reserved for future use.27260x0RDOWNSTREAM_COMPO_PRESENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5827Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component, if any, connected to the Link; defined values are: - 000b: Link Down – Presence Not Determined - 001b: Link Down – Component Not Present indicates the Downstream Port (DP) has determined that a Downstream Component is not present - 010b: Link Down – Component Present indicates the DP has determined that a Downstream Component is present, but the Data Link Layer is not active - 011b: Reserved - 100b: Link Up – Component Presentindicates the DP has determined that a Downstream Component is present, but no DRS Message has been received since the Data Link Layer became active - 101b: Link Up – Component Present and DRS Received indicates the DP has received a DRS Message since the Data Link Layer became active - 110b: Reserved - 111b: ReservedComponent Presence state must be determined by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism implemented for the Link. If no out-of-band presence detect mechanism is implemented, then Component Presence state must be determined solely by the Physical Layer in-band presence detect mechanism.This field must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This field is RsvdZ for all other Functions.30280x0RDRS_MESSAGE_RECEIVEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5848DRS Message Received. This bit must be set whenever the Port receives a DRS Message.This bit must be cleared in DL_Down.This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This bit is RsvdZ for all other Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: RW1C 31310x0R/W1CgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAPPF0_MSIX_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr60520xB0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAPPF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr59410x0R/W0x00800011PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5869MSI-X Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x11RPCI_MSIX_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5885MSI-X Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x00RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5910MSI-X Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5918Reserved for future use.29270x0RPCI_MSIX_FUNCTION_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5931Function Mask.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30300x0R/WPCI_MSIX_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5940MSI-X Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGMSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr59960x4R0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5971MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table BAR Indicator Register" (PCI_MSIX_BIR field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_BIR field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5995MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Offset" (PCI_MSIX_TABLE_OFFSET field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_OFFSET field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGMSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr60510x8R0x00008004PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6026MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA BIR" (PCI_MSIX_PBA_BIR field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_BIR field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6050MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA Offset" (PCI_MSIX_PBA_OFFSET field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_OFFSET field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00001000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAPPF0_AER_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr76520x100R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAPPF Advanced Error Reporting Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFAER_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr61110x0R0x14820001PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_AER_EXT_CAP_HDR_OFFAdvanced Error Reporting Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6078AER Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0001RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6094Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x2RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6110Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x148RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFUNCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr62870x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_STATUS_OFFUncorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6124Reserved for future use.300x0RDL_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6134Data Link Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.44R/W1CSURPRISE_DOWN_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6144Surprise Down Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.55R/W1CRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6152Reserved for future use.1160x00RPOIS_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6163Poisoned TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CFC_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6173Flow Control Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.1313R/W1CCMPLT_TIMEOUT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6184Completion Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CCMPLT_ABORT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6195Completer Abort Status.For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CUNEXP_CMPLT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6206Unexpected Completion Status.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/W1CREC_OVERFLOW_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6216Receiver Overflow Status.For a description of this standard PCIe register field, see the PCI Express Specification.1717R/W1CMALF_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6226Malformed TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.1818R/W1CECRC_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6240ECRC Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.Note:If CX_ECRC_ENABLE=0 the register field always reads 0.19190x0R/W1CUNSUPPORTED_REQ_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6251Unsupported Request Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.20200x0R/W1C--21210x0rINTERNAL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6270Uncorrectable Internal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.22220x0R/W1CRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6278Reserved for future use.23230x0R--26240x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6286Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFUNCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr64880x8R/W0x00400000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_MASK_OFFUncorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6300Reserved for future use.300x0RDL_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6311Data Link Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x0R/WSURPRISE_DOWN_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6328Surprise Down Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky.550x0R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6336Reserved for future use.1160x00RPOIS_TLP_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6347Poisoned TLP Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6358Flow Control Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x0R/WCMPLT_TIMEOUT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6369Completion Timeout Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6380Completer Abort Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6391Unexpected Completion Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6402Receiver Overflow Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x0R/WMALF_TLP_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6413Malformed TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x0R/WECRC_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6427ECRC Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6438Unsupported Request Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/WACS_VIOLATION_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6460ACS Violation Mask.Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors.The bit is Read-Only Zero for upstream ports, when ACS P2P Egress Control Enable is not set.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.21210x0RINTERNAL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6471Uncorrectable Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6479Reserved for future use.23230x0R--26240x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6487Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFUNCORR_ERR_SEV_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr66820xCR/W0x00462030PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_SEV_OFFUncorrectable Error Severity Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6501Reserved for future use.300x0RDL_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6512Data Link Protocol Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x1R/WSURPRISE_DOWN_ERR_SVRITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6529Surprise Down Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky.550x1R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6537Reserved for future use.1160x00RPOIS_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6548Poisoned TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6559Flow Control Protocol Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCMPLT_TIMEOUT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6570Completion Timeout Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6581Completer Abort Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6592Unexpected Completion Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6603Receiver Overflow Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x1R/WMALF_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6614Malformed TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x1R/WECRC_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6628ECRC Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6639Unsupported Request Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/W--21210x0rINTERNAL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6650Uncorrectable Internal Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6658Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6673AtomicOp Egress Blocked Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6681Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr68000x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_CORR_ERR_STATUS_OFFCorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6698Receiver Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6706Reserved for future use.510x00RBAD_TLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6717Bad TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CBAD_DLLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6728Bad DLLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.770x0R/W1CREPLAY_NO_ROLEOVER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6739REPLAY_NUM Rollover Status.For a description of this standard PCIe register field, see the PCI Express Specification.880x0R/W1CRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6747Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6758Replay Timer Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CADVISORY_NON_FATAL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6769Advisory Non-Fatal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.13130x0R/W1CCORRECTED_INT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6780Corrected Internal Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CHEADER_LOG_OVERFLOW_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6791Header Log Overflow Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6799Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr69180x14R/W0x0000e000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_CORR_ERR_MASK_OFFCorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6816Receiver Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6824Reserved for future use.510x00RBAD_TLP_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6835Bad TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WBAD_DLLP_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6846Bad DLLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x0R/WREPLAY_NO_ROLEOVER_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6857REPLAY_NUM Rollover Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6865Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6876Replay Timer Timeout Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WADVISORY_NON_FATAL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6887Advisory Non-Fatal Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCORRECTED_INT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6898Corrected Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x1R/WHEADER_LOG_OVERFLOW_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6909Header Log Overflow Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x1R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6917Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFADV_ERR_CAP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70290x18R/W0x000000a0PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFFAdvanced Error Capabilities and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_ERR_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6937First Error Pointer.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.400x00RECRC_GEN_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6949ECRC Generation Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RECRC_GEN_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6960ECRC Generation Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WECRC_CHECK_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6972ECRC Check Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x1RECRC_CHECK_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6983ECRC Check Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WMULTIPLE_HEADER_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr6995Multiple Header Recording Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.990x0RMULTIPLE_HEADER_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7010Multiple Header Recording Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.10100x0R--11110x0rCTO_PRFX_HDR_LOG_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7020TLP Prefix Log Present.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7028Reserved for future use.31130x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFHDR_LOG_0_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70880x1CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_0_OFFHeader Log Register 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7048Byte 0 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFIRST_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7061Byte 1 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFIRST_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7074Byte 2 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFIRST_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7087Byte 3 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFHDR_LOG_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr71470x20R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_1_OFFHeader Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseSECOND_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7107Byte 0 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RSECOND_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7120Byte 1 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RSECOND_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7133Byte 2 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RSECOND_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7146Byte 3 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFHDR_LOG_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr72060x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_2_OFFHeader Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseTHIRD_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7166Byte 0 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RTHIRD_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7179Byte 1 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RTHIRD_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7192Byte 2 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RTHIRD_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7205Byte 3 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFHDR_LOG_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr72650x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_3_OFFHeader Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFOURTH_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7225Byte 0 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFOURTH_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7238Byte 1 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFOURTH_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7251Byte 2 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFOURTH_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7264Byte 3 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFFROOT_ERR_CMD_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr73060x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_ROOT_ERR_CMD_OFFRoot Error Command Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCORR_ERR_REPORTING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7279Correctable Error Reporting Enable.For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/WNON_FATAL_ERR_REPORTING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7288Non-Fatal Error Reporting Enable.For a description of this standard PCIe register field, see the PCI Express Specification.110x0R/WFATAL_ERR_REPORTING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7297Fatal Error Reporting Enable.For a description of this standard PCIe register field, see the PCI Express Specification.220x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7305Reserved for future use.3130x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFFROOT_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr74140x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_ROOT_ERR_STATUS_OFFRoot Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseERR_COR_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7322Correctable Error Received.For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CMUL_ERR_COR_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7333Multiple Correctable Errors Received.For a description of this standard PCIe register field, see the PCI Express Specification.110x0R/W1CERR_FATAL_NON_FATAL_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7344Fatal or Non-Fatal Error Received.For a description of this standard PCIe register field, see the PCI Express Specification.220x0R/W1CMUL_ERR_FATAL_NON_FATAL_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7355Multiple Fatal or Non-Fatal Errors Received.For a description of this standard PCIe register field, see the PCI Express Specification.330x0R/W1CFIRST_UNCORR_FATALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7366First Uncorrectable Error is Fatal.For a description of this standard PCIe register field, see the PCI Express Specification.440x0R/W1CNON_FATAL_ERR_MSG_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7377One or more Non-Fatal Error Messages Received.For a description of this standard PCIe register field, see the PCI Express Specification.550x0R/W1CFATAL_ERR_MSG_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7388One or more Fatal Error Messages Received.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7396Reserved for future use.2670x00000RADV_ERR_INT_MSG_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7413Advanced Error Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFFERR_SRC_ID_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr74470x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_ERR_SRC_ID_OFFError Source Identification Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseERR_COR_SOURCE_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7433Source of Correctable Error.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1500x0000RERR_FATAL_NON_FATAL_SOURCE_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7446Source of Fatal/Non-Fatal Error.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFTLP_PREFIX_LOG_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr74980x38R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFFTLP Prefix Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_1_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7464Byte 0 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_1_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7475Byte 1 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_1_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7486Byte 2 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_1_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7497Byte 3 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFTLP_PREFIX_LOG_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr75490x3CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFFTLP Prefix Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_2_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7515Byte 0 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_2_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7526Byte 1 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_2_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7537Byte 2 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_2_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7548Byte 3 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFTLP_PREFIX_LOG_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr76000x40R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFFTLP Prefix Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_3_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7566Byte 0 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_3_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7577Byte 1 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_3_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7588Byte 2 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_3_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7599Byte 3 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFTLP_PREFIX_LOG_4_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr76510x44R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFFTLP Prefix Log Register 4.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_4_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7617Byte 0 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_4_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7628Byte 1 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_4_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7639Byte 2 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_4_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7650Byte 3 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAPPF0_VC_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr86440x148R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAPVirtual Channel Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_BASEregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_BASEVC_BASEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr77110x0R0x19810002PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_BASEVC Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PCIE_EXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7678VC Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0002RVC_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7694Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVC_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7710Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x198RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1VC_CAPABILITIES_REG_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr77810x4R0x00000003PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_1Port VC Capability Register 1.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_EXT_VC_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7726Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.200x3RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7733Reserved for future use.330x0RVC_LOW_PRI_EXT_VC_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7748Low Priority Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7755Reserved for future use.770x0RVC_REFERENCE_CLOCKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7764Reference Clock.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0RVC_PORT_ARBI_TBL_ENTRY_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7773Port Arbitration Table Entry Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.11100x0RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7780Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2VC_CAPABILITIES_REG_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr78190x8R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_2Port VC Capability Register 2.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_ARBI_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7802VC Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x1RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7809Reserved for future use.2340x00000RVC_ARBI_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7818VC Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGVC_STATUS_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr78700xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_STATUS_CONTROL_REGPort VC Control and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_LOAD_VC_ARBI_TABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7834Requests Hardware to Load VC Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_ARBI_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7843VC Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.310x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7851Reserved for future use.1540x000RVC_ARBI_TABLE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7861VC Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7869Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0RESOURCE_CAP_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr79350x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC0VC Resource Capability Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7885Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7892Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7905Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7918Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7925Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7934Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0RESOURCE_CON_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr80240x14R/W0x800000ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC0VC Resource Control Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7950Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RVC_TC_MAP_VC0_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7959Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x7fR/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7967Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7977Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7987Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr7995Reserved for future use.23180x00RVC_ID_VCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8005VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8013Reserved for future use.30270x0RVC_ENABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8023VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0RESOURCE_STATUS_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr80640x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0VC Resource Status Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8037Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8046Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8056VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8063Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1RESOURCE_CAP_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr81290x1CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC1VC Resource Capability Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8079VC1 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8086Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8099VC1 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8112VC1 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8119Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8128VC1 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1RESOURCE_CON_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr82170x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC1VC Resource Control Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8144VC1 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC1_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8153VC1 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8161Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8171VC1 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8181VC1 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8189Reserved for future use.23200x0RVC_ID_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8199VC1 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8207Reserved for future use.30270x0RVC_ENABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8216VC1 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1RESOURCE_STATUS_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr82570x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1VC Resource Status Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8230Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8239VC1 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8249VC1 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8256Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2RESOURCE_CAP_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr83220x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC2VC Resource Capability Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8272VC2 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8279Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8292VC2 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8305VC2 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8312Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8321VC2 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2RESOURCE_CON_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr84100x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC2VC Resource Control Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8337VC2 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC2_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8346VC2 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8354Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8364VC2 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8374VC2 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8382Reserved for future use.23200x0RVC_ID_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8392VC2 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8400Reserved for future use.30270x0RVC_ENABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8409VC2 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2RESOURCE_STATUS_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr84500x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2VC Resource Status Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8423Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8432VC2 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8442VC2 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8449Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3RESOURCE_CAP_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr85150x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC3VC Resource Capability Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8465VC3 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8472Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8485VC3 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8498VC3 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8505Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8514VC3 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3RESOURCE_CON_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr86030x38R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC3VC Resource Control Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8530VC3 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC3_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8539VC3 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8547Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8557VC3 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8567VC3 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8575Reserved for future use.23200x0RVC_ID_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8585VC3 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8593Reserved for future use.30270x0RVC_ENABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8602VC3 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3RESOURCE_STATUS_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr86430x3CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3VC Resource Status Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8616Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8625VC3 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8635VC3 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8642Reserved for future use.31180x0000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAPPF0_SPCIE_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr94840x198R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAPSecondary PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGSPCIE_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr87030x0R0x1b810019PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REGSPCIE Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8670Secondary PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0019RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8686Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8702Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1b8RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGLINK_CONTROL3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr87430x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_LINK_CONTROL3_REGLink Control 3 Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalsePERFORM_EQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8721Perform Equalization.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 00R/WEQ_REQ_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8734Link Equalization Request Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8742Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGLANE_ERR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr87680x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_LANE_ERR_STATUS_REGLane Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseLANE_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8759Lane Error Status Bits per Lane.For a description of this standard PCIe register field, see the PCI Express Specification.700x00R/W1CRSVDP_LANE_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8767Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGSPCIE_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr89430xCR0x7f7f7f7fPE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REGLane Equalization Control Register for lanes 1 and 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8789Downstream Port 8.0 GT/s Transmitter Preset 0.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8804Downstream Port 8.0 GT/s Receiver Preset Hint 0.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8811Reserved for future use.770x0RUSP_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8831Upstream Port 8.0 GT/s Transmitter Preset 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8851Upstream Port 8.0 GT/s Receiver Preset Hint 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8858Reserved for future use.15150x0RDSP_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8873Downstream Port 8.0 GT/s Transmitter Preset 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8888Downstream Port 8.0 GT/s Receiver Preset Hint 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8895Reserved for future use.23230x0RUSP_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8915Upstream Port 8.0 GT/s Transmitter Preset 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8935Upstream Port 8.0 GT/s Receiver Preset Hint 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8942Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGSPCIE_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr91230x10R0x7f7f7f7fPE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8969Downstream Port 8.0 GT/s Transmitter Preset2.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8984Downstream Port 8.0 GT/s Receiver Preset Hint2.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr8991Reserved for future use.770x0RUSP_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9011Upstream Port 8.0 GT/s Transmitter Preset2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9031Upstream Port 8.0 GT/s Receiver Preset Hint2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9038Reserved for future use.15150x0RDSP_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9053Downstream Port 8.0 GT/s Transmitter Preset3.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9068Downstream Port 8.0 GT/s Receiver Preset Hint3.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9075Reserved for future use.23230x0RUSP_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9095Upstream Port 8.0 GT/s Transmitter Preset3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9115Upstream Port 8.0 GT/s Receiver Preset Hint3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9122Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGSPCIE_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr93030x14R0x7f7f7f7fPE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9149Downstream Port 8.0 GT/s Transmitter Preset4.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9164Downstream Port 8.0 GT/s Receiver Preset Hint4.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9171Reserved for future use.770x0RUSP_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9191Upstream Port 8.0 GT/s Transmitter Preset4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9211Upstream Port 8.0 GT/s Receiver Preset Hint4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9218Reserved for future use.15150x0RDSP_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9233Downstream Port 8.0 GT/s Transmitter Preset5.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9248Downstream Port 8.0 GT/s Receiver Preset Hint5.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9255Reserved for future use.23230x0RUSP_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9275Upstream Port 8.0 GT/s Transmitter Preset5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9295Upstream Port 8.0 GT/s Receiver Preset Hint5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9302Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGSPCIE_CAP_OFF_18H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr94830x18R0x7f7f7f7fPE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9329Downstream Port 8.0 GT/s Transmitter Preset6.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9344Downstream Port 8.0 GT/s Receiver Preset Hint6.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9351Reserved for future use.770x0RUSP_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9371Upstream Port 8.0 GT/s Transmitter Preset6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9391Upstream Port 8.0 GT/s Receiver Preset Hint6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9398Reserved for future use.15150x0RDSP_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9413Downstream Port 8.0 GT/s Transmitter Preset7.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9428Downstream Port 8.0 GT/s Receiver Preset Hint7.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9435Reserved for future use.23230x0RUSP_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9455Upstream Port 8.0 GT/s Transmitter Preset7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9475Upstream Port 8.0 GT/s Receiver Preset Hint7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9482Reserved for future use.31310x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAPPF0_PL16G_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr99670x1B8R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAPPhysical Layer 16.0 GT/s Extended Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPL16G_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr95430x0R0x1e010026PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REGPhysical Layer 16.0 GT/s Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9510PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0026RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9526Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9542Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1e0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPL16G_CAPABILITY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr95570x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAPABILITY_REG16.0 GT/s Capabilities Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9556Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPL16G_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr95710x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CONTROL_REG16.0 GT/s Control Register .For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9570Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPL16G_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr96520xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_STATUS_REG16.0 GT/s Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEQ_16G_CPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9590Equalization 16.0GT/s Complete.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.000x0REQ_16G_CPL_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9604Equalization 16.0GT/s Phase 1 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.110x0REQ_16G_CPL_P2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9618Equalization 16.0GT/s Phase 2 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.220x0REQ_16G_CPL_P3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9632Equalization 16.0GT/s Phase 3 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.330x0RLINK_EQ_16G_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9643Link Equalization Request 16.0GT/s.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.440x0R/W1CRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9651Reserved for future use.3150x0000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPL16G_LC_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr96770x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG16.0 GT/s Local Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseLC_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9668Local Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_LC_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9676Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr97020x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG16.0 GT/s First Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseFIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9693First Retimer Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_FIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9701Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr97280x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG16.0 GT/s Second Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseSECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9719Second Retimer Data Parity Mismatch Status .For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_SECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9727Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPL16G_CAP_OFF_20H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr98470x20R0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG16.0 GT/s Lane Equalization Control Register for Lane 0-3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9748Downstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 300xfRUSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9762Upstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 740xfRDSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9776Downstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 1180xfRUSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9790Upstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 15120xfRDSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9804Downstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 19160xfRUSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9818Upstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 23200xfRDSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9832Downstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 27240xfRUSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9846Upstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31280xfRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPL16G_CAP_OFF_24H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr99660x24R0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG16.0 GT/s Lane Equalization Control Register for Lane 4-7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9867Downstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 300xfRUSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9881Upstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 740xfRDSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9895Downstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 1180xfRUSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9909Upstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 15120xfRDSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9923Downstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 19160xfRUSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9937Upstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 23200xfRDSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9951Downstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 27240xfRUSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9965Upstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31280xfRgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAPPF0_MARGIN_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr109560x1E0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAPMargining Extended Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGMARGIN_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr100260x0R0x20810027PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REGMargining Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr9993PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0027RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10009Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10025Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x208RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGMARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr100830x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REGMargining Port Capabilities and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseMARGINING_USES_DRIVER_SOFTWAREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10048Margining uses Driver Software.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10055Reserved for future use.1510x0000RMARGINING_READYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10065Margining Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1616RMARGINING_SOFTWARE_READYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10075Margining Software Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10082Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGMARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr101920x8R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REGMargining Lane Control and Status Register for Lane 0.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10097Receiver Number for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10107Margin Type for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10117Usage Model for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10125Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10135Margin Payload for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10147Receiver Number(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10159Margin Type(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10171Usage Model(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10179Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10191Margin Payload(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGMARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr103010xCR/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REGMargining Lane Control and Status Register for Lane 1.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10206Receiver Number for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10216Margin Type for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10226Usage Model for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10234Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10244Margin Payload for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10256Receiver Number(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10268Margin Type(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10280Usage Model(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10288Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10300Margin Payload(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGMARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr104100x10R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REGMargining Lane Control and Status Register for Lane 2.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10315Receiver Number for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10325Margin Type for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10335Usage Model for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10343Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10353Margin Payload for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10365Receiver Number(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10377Margin Type(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10389Usage Model(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10397Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10409Margin Payload(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGMARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr105190x14R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REGMargining Lane Control and Status Register for Lane 3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10424Receiver Number for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10434Margin Type for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10444Usage Model for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10452Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10462Margin Payload for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10474Receiver Number(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10486Margin Type(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10498Usage Model(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10506Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10518Margin Payload(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGMARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr106280x18R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REGMargining Lane Control and Status Register for Lane 4.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10533Receiver Number for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10543Margin Type for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10553Usage Model for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10561Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10571Margin Payload for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10583Receiver Number(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10595Margin Type(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10607Usage Model(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10615Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10627Margin Payload(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGMARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr107370x1CR/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REGMargining Lane Control and Status Register for Lane 5.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10642Receiver Number for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10652Margin Type for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10662Usage Model for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10670Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10680Margin Payload for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10692Receiver Number(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10704Margin Type(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10716Usage Model(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10724Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10736Margin Payload(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGMARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr108460x20R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REGMargining Lane Control and Status Register for Lane 6.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10751Receiver Number for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10761Margin Type for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10771Usage Model for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10779Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10789Margin Payload for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10801Receiver Number(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10813Margin Type(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10825Usage Model(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10833Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10845Margin Payload(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGMARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr109550x24R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REGMargining Lane Control and Status Register for Lane 7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10860Receiver Number for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10870Margin Type for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10880Usage Model for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10888Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10898Margin Payload for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10910Receiver Number(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10922Margin Type(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10934Usage Model(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10942Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10954Margin Payload(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAPPF0_TPH_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr112370x208R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAPPF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGTPH_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr110150x0R0x29c10017PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REGTPH Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCIE_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10982TPH Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0017RTPH_REQ_CAP_VERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr10998Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RTPH_REQ_NEXT_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11014Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x29cRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGTPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr111540x4R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_REQ_CAP_REG_REGTPH Requestor Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11037No ST Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11053Interrupt Vector Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11069Device Specific Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11076Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11092Extended TPH Requester Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11108ST Table Location Bit 0.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11124ST Table Location Bit 1.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11131Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11146ST Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11153Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGTPH_REQ_CONTROL_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr111990x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REGTPH Requestor Control Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_MODE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11173ST Mode Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11181Reserved for future use.730x00RTPH_REQ_CTRL_REQ_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11190TPH Requester Enable Bit.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11198Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0TPH_ST_TABLE_REG_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr112360xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_ST_TABLE_REG_0TPH ST Table Register 0.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_TABLE_LOWER_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11219ST Table 0 Lower Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: this field is RW or Tie to 0 by table size configure 700x00R/WTPH_REQ_ST_TABLE_HIGHER_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11235ST Table 0 Upper Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: this field is RW or Tie to 0 by table size configure 1580x00R--31160x0rgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAPPF0_L1SUB_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr116770x29CR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAPL1 Substates Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGL1SUB_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr11311L1 Substates Extended Capability Header provides capbility ID, capability version and next offset value for L1 Substates.0x0R0x2ac1001ePE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REGL1 Substates Extended Capability Header.This register provides capbility ID, capability version and next offset value for L1 Substates.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11268L1SUB Extended Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for L1 PM Substates is 001Eh.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001eRCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11285Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11310Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2acRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGL1SUB_CAPABILITY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr11476This register provides extended capability of L1 Substates.0x4R/W0x00380a1fPE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REGL1 Substates Capability Register.This register provides extended capability of L1 Substates.falsefalsefalsefalseL1_2_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11329PCI-PM L12 Supported.When Set this bit indicates that PCI-PM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 000x1R/WL1_1_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11342PCI-PM L11 Supported.When Set this bit indicates that PCI-PM L1.1 is supported, and must be Set by all Ports implementing L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 110x1R/WL1_2_ASPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11354ASPM L12 Supported.When Set this bit indicates that ASPM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 220x1R/WL1_1_ASPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11366ASPM L11 Supported.When Set this bit indicates that ASPM L1.1 is supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 330x1R/WL1_PMSUB_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11379L1 PM Substates ECN Supported.When Set this bit indicates that this Port supports L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11387Reserved for future use.750x0RCOMM_MODE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11406Port Common Mode Restore Time.Time (in us) required for this Port to re-establish common mode.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 1580x0aR/WPWR_ON_SCALE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11433Port T Power On Scale.Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register.Range of values are given below.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 17160x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11441Reserved for future use.18180x0RPWR_ON_VALUE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11467Port T Power On Value.Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. Default value is 00101b.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 23190x07R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11475Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGL1SUB_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr11596This register provides Controls to extended capability.0x8R/W0x00000a00PE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL1_REGL1 Substates Control 1 Register.This register provides Controls to extended capability.falsefalsefalsefalseL1_2_PCIPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11492PCI-PM L12 Enable.When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.000x0R/WL1_1_PCIPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11501PCI-PM L11 Enable.When Set this bit enables PCI-PM L1.1. Default value is 0b.110x0R/WL1_2_ASPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11511ASPM L12 Enable.When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.220x0R/WL1_1_ASPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11521ASPM L11 Enable.When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11529Reserved for future use.740x0RT_COMMON_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11548Common Mode Restore Time.Sets value of TCOMMONMODE (in μs), which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports.Default value is implementation specific.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RW : RSVDP 1580x0aR/WL1_2_TH_VALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11567LTR L12 Threshold Value.Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b.Required for all Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 25160x000R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11575Reserved for future use.28260x0RL1_2_TH_SCAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11595LTR L12 Threshold Scale.This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field.Required for all Ports Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 31290x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGL1SUB_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr11676This register provides Controls to extended capability.0xCR/W0x00000028PE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL2_REGL1 Substates Control 2 Register.This register provides Controls to extended capability.falsefalsefalsefalseT_POWER_ON_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11632T Power On Scale.Specifies the scale used for T_POWER_ON Value.Range of values are given below.Required for all Ports that support L1.2, otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 100x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11640Reserved for future use.220x0RT_POWER_ON_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11667T Power On Value.Along with the T_POWER_ON Scale sets the minimum amount of time (in μs) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b.T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.Required for all Ports that support L1.2, otherwise this field is of type RsvdP.This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 730x05R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11675Reserved for future use.3180x000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAPPF0_FRSQ_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr118660x2ACR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_FRSQ_CAPPF FRSQ Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFFFRSQ_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr117360x0R0x2c410021PE0_DWC_pcie_ctl_AXI_Slave_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFFFRS Queuing Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRSQ_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11703PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0021RFRSQ_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11719Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RFRSQ_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11735Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2c4RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFFFRSQ_CAP_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr117810x4R0x00000008PE0_DWC_pcie_ctl_AXI_Slave_PF0_FRSQ_CAP_FRSQ_CAP_OFFFRS Queuing Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRSQ_MAX_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11751FRS Queue Max Depth.For a description of this standard PCIe register field, see the PCI Express Specification.1100x008RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11758Reserved for future use.15120x0RFRS_INT_MESSAGE_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11773FRS Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11780Reserved for future use.31210x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFFFRSQ_CONTROL_FRSQ_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr118340x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFFFRS Queuing Status and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRS_MESSAGE_RECEIVEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11797FRS Message Received.For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CFRS_MESSAGE_OVERFLOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11808FRS Message Overflow.For a description of this standard PCIe register field, see the PCI Express Specification.110x0R/W1CRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11816Reserved for future use.1520x0000RFRS_INTERRUPT_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11825FRS Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11833Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFFFRS_MESSAGE_QUEUE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr118650xCRPE0_DWC_pcie_ctl_AXI_Slave_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFFFRS Message Queue Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRS_MESSAGE_QUE_FUNC_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11848FRS Message Queue Function ID.For a description of this standard PCIe register field, see the PCI Express Specification.150RFRS_MESSAGE_QUE_REASONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11856FRS Message Queue Reason.For a description of this standard PCIe register field, see the PCI Express Specification.1916RFRS_MESSAGE_QUE_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11864FRS Message Queue Depth.For a description of this standard PCIe register field, see the PCI Express Specification.3120RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAPPF0_RAS_DES_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr151060x2C4R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAPRAS D.E.S. Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGRAS_DES_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr119250x0R0x3c41000bPE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REGVendor-Specific Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11892PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11908Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11924Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3c4RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGVENDOR_SPECIFIC_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr119590x4R0x10040002PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REGVendor-Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11940VSEC ID.For a description of this standard PCIe register field, see the PCI Express Specification.1500x0002RVSEC_REVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11949VSEC Rev.For a description of this standard PCIe register field, see the PCI Express Specification.19160x4RVSEC_LENGTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr11958VSEC Length.For a description of this standard PCIe register field, see the PCI Express Specification.31200x100RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGEVENT_COUNTER_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr121060x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REGEvent Counter Control.This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.falsefalsefalsefalseEVENT_COUNTER_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12000Event Counter Clear.Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code.The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved100x0WEVENT_COUNTER_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12026Event Counter Enable.Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.By default, all event counters are disabled.You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes.You can enable/disable all event counters by writing the 'all on' or 'all off' codes.The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on420x0WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12034Reserved for future use.650x0REVENT_COUNTER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12049Event Counter Status.This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECTNote: This register field is sticky.770x0REVENT_COUNTER_LANE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12066Event Counter Lane Select.This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12074Reserved for future use.15120x0REVENT_COUNTER_EVENT_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12097Event Counter Data Select.This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the GroupFor example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLPFor detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.Note: This register field is sticky.27160x000R/WRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12105Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGEVENT_COUNTER_DATA_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr121310xCR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REGEvent Counter Data.This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEVENT_COUNTER_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12130Event Counter Data.This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGNote: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGTIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr122470x10R/W0x00000100PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REGTime-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIMER_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12155Timer Start. - 1: Start/Restart - 0: StopThis bit will be cleared automatically when the measurement is finished.Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12163Reserved for future use.710x00RTIME_BASED_DURATION_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12185Time-based Duration Select.Selects the duration of time-based analysis.When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - 0xff: 4us (Debug purpose) - Else: ReservedNote: This register field is sticky.1580x01R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12193Reserved for future use.23160x00RTIME_BASED_REPORT_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12246Time-based Report Select.Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA.Each type of data is measured using one of three types of units: - Core_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Core_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate). Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x10] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATACore_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 - 0x07: Configuration/Recovery - 0x08: TxL0s and RxL0sAux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 - 0x09: L1 auxCore_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate) - 0x10: Duration of 1 cycle - 0x11: TxL0s - 0x12: RxL0s - 0x13: L0 - 0x14: L1 - 0x17: Configuration/Recovery - 0x18: TxL0s and RxL0sData Bytes - 0x20: Tx PCIe TLP data payload Bytes - 0x21: Rx PCIe TLP data payload Bytes - 0x22: Tx CCIX TLP data payload Bytes - 0x23: Rx CCIX TLP data payload Bytes - Else: RsvdNote: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGTIME_BASED_ANALYSIS_DATA_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr122740x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REGTime-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12273Time Based Analysis Data.This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.The results are cleared when next measurement starts.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGTIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr122950x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REGUpper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATA_63_32PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12294Upper 32 bits of Time Based Analysis Data.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGEINJ_ENABLE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr124320x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ_ENABLE_REGError Injection Enable.Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REGAfter the errors have been inserted by controller, it will clear each bit here.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_INJECTION0_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12328Error Injection0 Enable (CRC Error).Enables insertion of errors into various CRC.For more details, see the EINJ0_CRC_REG register.Note: This register field is sticky.000x0R/WERROR_INJECTION1_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12342Error Injection1 Enable (Sequence Number Error).Enables insertion of errors into sequence numbers.For more details, see the EINJ1_SEQNUM_REG register.Note: This register field is sticky.110x0R/WERROR_INJECTION2_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12356Error Injection2 Enable (DLLP Error).Enables insertion of DLLP errors.For more details, see the EINJ2_DLLP_REG register.Note: This register field is sticky.220x0R/WERROR_INJECTION3_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12372Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).Enables DataK masking of special symbols or the breaking of the sync header.For more details, see the EINJ3_SYMBOL_REG register.Note: This register field is sticky.330x0R/WERROR_INJECTION4_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12386Error Injection4 Enable (FC Credit Update Error).Enables insertion of errors into UpdateFCs.For more details, see the EINJ4_FC_REG register.Note: This register field is sticky.440x0R/WERROR_INJECTION5_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12400Error Injection5 Enable (TLP Duplicate/Nullify Error).Enables insertion of duplicate/nullified TLPs.For more details, see the EINJ5_SP_TLP_REG register.Note: This register field is sticky.550x0R/WERROR_INJECTION6_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12423Error Injection6 Enable (Specific TLP Error).Enables insertion of errors into the packets that you select.You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0.For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.Note: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12431Reserved for future use.3170x0000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGEINJ0_CRC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr125020x34R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ0_CRC_REGError Injection Control 0 (CRC Error).Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side.falsefalsefalsefalseEINJ0_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12470Error injection count.Indicates the number of errors.This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ0_CRC_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12493Error injection type.Selects the type of CRC error to be inserted.Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b)Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: ReservedNote: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12501Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGEINJ1_SEQNUM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr126000x38R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REGError Injection Control 1 (Sequence Number Error).Controls the sequence number of the specific TLPs and ACK/NAK DLLPs.Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048falsefalsefalsefalseEINJ1_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12537Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ1_SEQNUM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12549Sequence number type.Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# ErrorNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12557Reserved for future use.1590x00REINJ1_BAD_SEQNUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12591Bad sequence number.Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link.Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12599Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGEINJ2_DLLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr126600x3CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ2_DLLP_REGError Injection Control 2 (DLLP Error).Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.falsefalsefalsefalseEINJ2_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12637Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'.This register is affected only when EINJ2_DLLP_TYPE =2'10b.Note: This register field is sticky.700x00R/WEINJ2_DLLP_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12651DLLP Type.Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: ReservedNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12659Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGEINJ3_SYMBOL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr127200x40R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REGError Injection Control 3 (Symbol Error).When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.When 128b/130b encoding is used, this register controls error insertion into the sync-header.falsefalsefalsefalseEINJ3_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12688Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ3_SYMBOL_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12711Error Type.8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set)128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12719Reserved for future use.31110x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGEINJ4_FC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr128250x44R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ4_FC_REGError Injection Control 4 (FC Credit Error).Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data creditThese errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.falsefalsefalsefalseEINJ4_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12751Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ4_UPDFC_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12769Update-FC type.Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12777Reserved for future use.11110x0REINJ4_VC_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12788VC Number.Indicates target VC Number.Note: This register field is sticky.14120x0R/WRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12796Reserved for future use.15150x0REINJ4_BAD_UPDFC_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12816Bad update-FC credit value.Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12824Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGEINJ5_SP_TLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr128820x48R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REGError Injection Control 5 (Specific TLP Error).Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.falsefalsefalsefalseEINJ5_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12859Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ5_SPECIFIED_TLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12873Specified TLP.Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer).Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12881Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGEINJ6_COMPARE_POINT_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr129200x4CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REGError Injection Control 6 (Compare Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12919Packet Compare Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGEINJ6_COMPARE_POINT_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr129580x50R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REGError Injection Control 6 (Compare Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12957Packet Compare Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGEINJ6_COMPARE_POINT_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr129940x54R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REGError Injection Control 6 (Compare Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr12993Packet Compare Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGEINJ6_COMPARE_POINT_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr130320x58R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REGError Injection Control 6 (Compare Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13031Packet Compare Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGEINJ6_COMPARE_VALUE_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr130660x5CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REGError Injection Control 6 (Compare Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13065Packet Compare Value: 1st DWORD.Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGEINJ6_COMPARE_VALUE_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr131000x60R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REGError Injection Control 6 (Compare Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13099Packet Compare Value: 2nd DWORD.Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGEINJ6_COMPARE_VALUE_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr131340x64R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REGError Injection Control 6 (Compare Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13133Packet Compare Value: 3rd DWORD.Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGEINJ6_COMPARE_VALUE_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr131680x68R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REGError Injection Control 6 (Compare Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13167Packet Compare Value: 4th DWORD.Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGEINJ6_CHANGE_POINT_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr132000x6CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REGError Injection Control 6 (Change Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13199Packet Change Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGEINJ6_CHANGE_POINT_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr132320x70R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REGError Injection Control 6 (Change Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13231Packet Change Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGEINJ6_CHANGE_POINT_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr132640x74R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REGError Injection Control 6 (Change Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13263Packet Change Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGEINJ6_CHANGE_POINT_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr132960x78R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REGError Injection Control 6 (Change Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13295Packet Change Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGEINJ6_CHANGE_VALUE_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr133310x7CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REGError Injection Control 6 (Change Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13330Packet Change Value: 1st DWORD.Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGEINJ6_CHANGE_VALUE_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr133660x80R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REGError Injection Control 6 (Change Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13365Packet Change Value: 2nd DWORD.Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGEINJ6_CHANGE_VALUE_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr134010x84R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REGError Injection Control 6 (Change Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13400Packet Change Value: 3rd DWORD.Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGEINJ6_CHANGE_VALUE_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr134360x88R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REGError Injection Control 6 (Change Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13435Packet Change Value: 4th DWORD.Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGEINJ6_TLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr135170x8CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_TLP_REGError Injection Control 6 (Packet Error).The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the this register.The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register.Only applies when EINJ6_INVERTED_CONTROL in this register =0.The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bitfalsefalsefalsefalseEINJ6_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13480Error Injection Count.Indicates the number of errors to insert.This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ6_INVERTED_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13493Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].Note: This register field is sticky.880x0R/WEINJ6_PACKET_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13508Packet type.Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: ReservedNote: This register field is sticky.1190x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13516Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGSD_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr136140xA0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_CONTROL1_REGSilicon Debug Control 1.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_DETECT_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13540Force Detect Lane.When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15Note: This register field is sticky.1500x0000R/WFORCE_DETECT_LANE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13554Force Detect Lane Enable.When this bit is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13562Reserved for future use.19170x0RTX_EIOS_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13587Number of Tx EIOS.This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification.2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 165.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32Note: This register field is sticky.21200x0R/WLOW_POWER_INTERVALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13605Low Power Entry Interval Time.Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640nsNote: This register field is sticky.23220x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13613Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGSD_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr137370xA4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_CONTROL2_REGSilicon Debug Control 2.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseHOLD_LTSSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13632Hold and Release LTSSM.For as long as this register is '1', the controller stays in the current LTSSM.Note: This register field is sticky.000x0R/WRECOVERY_REQUESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13645Recovery Request.When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.110x0WNOACK_FORCE_LINKDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13659Force LinkDown.When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.Note: This register field is sticky.220x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13667Reserved for future use.730x00RDIRECT_RECIDLE_TO_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13680Direct Recovery.Idle to Configuration.When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.Note: This register field is sticky.880x0R/WDIRECT_POLCOMP_TO_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13693Direct Polling.Compliance to Detect.When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.Note: This register field is sticky.990x0R/WDIRECT_LPBKSLV_TO_EXITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13707Direct Loopback Slave To Exit.When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.Note: This register field is sticky.10100x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13715Reserved for future use.15110x00RFRAMING_ERR_RECOVERY_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13728Framing Error Recovery Disable.This bit disables a transition to Recovery state when a Framing Error is occurred.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13736Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGSD_STATUS_L1LANE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr138690xB0R/W0x00180000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REGSilicon Debug Status(Layer1 Per-lane).This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseLANE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13762Lane Select.Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13770Reserved for future use.1540x000RPIPE_RXPOLARITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13785PIPE:RxPolarity.Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).Note: This register field is sticky.16160x0RPIPE_DETECT_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13800PIPE:Detect Lane.Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).Note: This register field is sticky.17170x0RPIPE_RXVALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13815PIPE:RxValid.Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).Note: This register field is sticky.18180x0RPIPE_RXELECIDLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13830PIPE:RxElecIdle.Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.19190x1RPIPE_TXELECIDLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13845PIPE:TxElecIdle.Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.20200x1RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13853Reserved for future use.23210x0RDESKEW_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13868Deskew Pointer.Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGSD_STATUS_L1LTSSM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr140180xB4R/W0x00000200PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REGSilicon Debug Status(Layer1 LTSSM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFRAMING_ERR_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13938First Framing Error Pointer.Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1.Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit controller only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder.Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS stateAll other values not listed above are Reserved.Note: This register field is sticky.600x00RFRAMING_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13949Framing Error.Indicates Framing Error detection status.770x0R/W1CPIPE_POWER_DOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13963PIPE:PowerDown.Indicates PIPE PowerDown signal.Note: This register field is sticky.1080x2RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13971Reserved for future use.14110x0RLANE_REVERSALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr13987Lane Reversal Operation.Receiver detected lane reversal.This field is only valid in the L0 LTSSM state.Note: This register field is sticky.15150x0RLTSSM_VARIABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14017LTSSM Variable.Indicates internal LTSSM variables defined in the PCI Express Base Specification.C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitionedM-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configurationNote: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGSD_STATUS_PM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr141590xB8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_PM_REGSilicon Debug Status(PM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseINTERNAL_PM_MSTATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14060Internal PM State(Master).Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP - 19h: WAIT_DSTATE_UPDATENote: This register field is sticky.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14068Reserved for future use.750x0RINTERNAL_PM_SSTATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14095Internal PM State(Slave).Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch: S_WAIT_LAST_PMDLLPNote: This register field is sticky.1180x0RPME_RESEND_FLAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14109PME Re-send flag.When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.12120x0R/W1CL1SUB_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14135L1Sub State.Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check clkreq_in_n is de-asserted for t_power_off time (only for L1.2, reduces to one cycle for L1.1) - 5h: S_L1_N : L1 substate, turn off txcommonmode circuits (L1.2 only) and rx electrical idle detection circuits - 6h: S_L1_N_EXIT : locally/remotely initiated exit, assert pclkreq, wait for pclkack - 7h: S_L1_N_ABORT : wait for pclkack when aborting an attempt to enter L1_NNote: This register field is sticky.15130x0RLATCHED_NFTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14150Latched N_FTS.Indicates the value of N_FTS in the received TS Ordered Sets from the Link PartnerNote: This register field is sticky.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14158Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGSD_STATUS_L2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr142400xBCR0x00fff000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L2_REGSilicon Debug Status(Layer2).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTX_TLP_SEQ_NOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14178Tx Tlp Sequence Number.Indicates next transmit sequence number for transmit TLP.Note: This register field is sticky.1100x000RRX_ACK_SEQ_NOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14192Tx Ack Sequence Number.Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.Note: This register field is sticky.23120xfffRDLCMSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14207DLCMSM.Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVENote: This register field is sticky.25240x0RFC_INIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14220FC_INIT1.Indicates the controller is in FC_INIT1(VC0) state.Note: This register field is sticky.26260x0RFC_INIT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14232FC_INIT2.Indicates the controller is in FC_INIT2(VC0) state.Note: This register field is sticky.27270x0RRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14239Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGSD_STATUS_L3FC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr143640xC0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REGSilicon Debug Status(Layer3 FC).The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HDFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseCREDIT_SEL_VCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14271Credit Select(VC).This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7Note: This register field is sticky.200x0R/WCREDIT_SEL_CREDIT_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14287Credit Select(Credit Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: TxNote: This register field is sticky.330x0R/WCREDIT_SEL_TLP_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14304Credit Select(TLP Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: CompletionNote: This register field is sticky.540x0R/WCREDIT_SEL_HDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14320Credit Select(HeaderData).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data CreditNote: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14328Reserved for future use.770x0RCREDIT_DATA0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14345Credit Data0.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed ValueNote: This register field is sticky.1980x000RCREDIT_DATA1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14363Credit Data1.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE).Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGSD_STATUS_L3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr144200xC4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3_REGSilicon Debug Status(Layer3).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseMFTLP_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14400First Malformed TLP Error Pointer.Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: ReservedNote: This register field is sticky.600x00RMFTLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14411Malformed TLP Status.Indicates malformed TLP has occurred.770x0R/W1CRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14419Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGSD_EQ_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr145600xD0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REGSilicon Debug EQ Control 1.This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LANE_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14448EQ Status Lane Select.Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WEQ_RATE_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14465EQ Status Rate Select.Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed (include ESM data rate) - 0x1: 16.0GT/s Speed (include ESM data rate) - 0x2: 32.0GT/s SpeedNote: This register field is sticky.540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14473Reserved for future use.760x0REXT_EQ_TIMEOUTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14497Extends EQ Phase2/3 Timeout.This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set, the value of EQ2/3 timeout is extended.EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeoutEQ Slave(DSP in EQ Phase2/USP in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No timeoutNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14505Reserved for future use.15100x00REVAL_INTERVAL_TIMEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14523Eval Interval Time.Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4usThis field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).Note: This register field is sticky.17160x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14531Reserved for future use.22180x00RFOM_TARGET_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14543FOM Target Enable.Enables the FOM_TARGET fields.Note: This register field is sticky.23230x0R/WFOM_TARGETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14559FOM Target.Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).Note: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGSD_EQ_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr147040xD4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REGSilicon Debug EQ Control 2.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_LOCAL_TX_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14582Force Local Transmitter Pre-cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.500x00R/WFORCE_LOCAL_TX_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14596Force Local Transmitter Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.1160x00R/WFORCE_LOCAL_TX_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14610Force Local Transmitter Post-Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.17120x00R/WFORCE_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14627Force Local Receiver Preset Hint.Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0R/WRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14635Reserved for future use.23210x0RFORCE_LOCAL_TX_PRESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14651Force Local Transmitter Preset.Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.27240x0R/WFORCE_LOCAL_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14665Force Local Transmitter Coefficient Enable.Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSORNote: This register field is sticky.28280x0R/WFORCE_LOCAL_RX_HINT_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14680Force Local Receiver Preset Hint Enable.Enables the FORCE_LOCAL_RX_HINT field.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.29290x0R/WFORCE_LOCAL_TX_PRESET_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14695Force Local Transmitter Preset Enable.Enables the FORCE_LOCAL_TX_PRESET field.If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14703Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGSD_EQ_CONTROL3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr147880xD8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REGSilicon Debug EQ Control 3.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_REMOTE_TX_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14726Force Remote Transmitter Pre-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.500x00R/WFORCE_REMOTE_TX_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14740Force Remote Transmitter Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.1160x00R/WFORCE_REMOTE_TX_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14754Force Remote Transmitter Post-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.17120x00R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14762Reserved for future use.27180x000RFORCE_REMOTE_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14779Force Remote Transmitter Coefficient Enable.Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSORThis function can only be used when GEN3_EQ_FB_MODE = 0000b(Direction Change)Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14787Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGSD_EQ_STATUS1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr149320xE0R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REGSilicon Debug EQ Status 1.This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENTFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_SEQUENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14818EQ Sequence.Indicates that the controller is starting the equalization sequence.Note: This register field is sticky.000x0REQ_CONVERGENCE_INFOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14837EQ Convergence Info.Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: ReservedThis bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.210x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14844Reserved for future use.330x0REQ_RULEA_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14865EQ Rule A Violation.Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.440x0REQ_RULEB_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14886EQ Rule B Violation.Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.550x0REQ_RULEC_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14907EQ Rule C Violation.Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.660x0REQ_REJECT_EVENTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14924EQ Reject Event.Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.770x0RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14931Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGSD_EQ_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr150200xE4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REGSilicon Debug EQ Status 2.This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LOCAL_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14957EQ Local Pre-Cursor.Indicates Local pre cursor coefficient value.Note: This register field is sticky.500x00REQ_LOCAL_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14970EQ Local Cursor.Indicates Local cursor coefficient value.Note: This register field is sticky.1160x00REQ_LOCAL_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14983EQ Local Post-Cursor.Indicates Local post cursor coefficient value.Note: This register field is sticky.17120x00REQ_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr14999EQ Local Receiver Preset Hint.Indicates Local Receiver Preset Hint value.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15006Reserved for future use.23210x0REQ_LOCAL_FOM_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15019EQ Local Figure of Merit.Indicates Local maximum Figure of Merit value.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGSD_EQ_STATUS3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr151050xE8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REGSilicon Debug EQ Status 3.This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_REMOTE_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15045EQ Remote Pre-Cursor.Indicates Remote pre cursor coefficient value.Note: This register field is sticky.500x00REQ_REMOTE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15058EQ Remote Cursor.Indicates Remote cursor coefficient value.Note: This register field is sticky.1160x00REQ_REMOTE_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15071EQ Remote Post-Cursor.Indicates Remote post cursor coefficient value.Note: This register field is sticky.17120x00REQ_REMOTE_LFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15084EQ Remote LF.Indicates Remote LF value.Note: This register field is sticky.23180x00REQ_REMOTE_FSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15097EQ Remote FS.Indicates Remote FS value.Note: This register field is sticky.29240x00RRSVDP_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15104Reserved for future use.31300x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAPPF0_VSECRAS_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr161590x3C4R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAPPF RAS Datapath Protection Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFRASDP_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr151660x0R0x3fc1000bPE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFFPCIe Extended capability ID, Capability version and Next capability offset.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15133PCI Express Extended Capability ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15149Capability Version.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15165Next Capability Offset.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3fcRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFRASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr152090x4R0x03810001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFFVendor Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15184VSEC ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1500x0001RVSEC_REVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15196VSEC Rev.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.19160x1RVSEC_LENGTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15208VSEC Length.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.31200x038RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFRASDP_ERROR_PROT_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr15415ECC error correction control0x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFFECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.falsefalsefalsefalseERROR_PROT_DISABLE_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15233Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.000x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_MASTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15244Error correction disable for AXI bridge master completion buffer.Note: This register field is sticky.110x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15255Error correction disable for AXI bridge outbound request path.Note: This register field is sticky.220x0R/WERROR_PROT_DISABLE_DMA_WRITEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15265Error correction disable for DMA write engine.Note: This register field is sticky.330x0R/WERROR_PROT_DISABLE_LAYER2_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15275Error correction disable for layer 2 Tx path.Note: This register field is sticky.440x0R/WERROR_PROT_DISABLE_LAYER3_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15285Error correction disable for layer 3 Tx path.Note: This register field is sticky.550x0R/WERROR_PROT_DISABLE_ADM_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15295Error correction disable for Adm Tx path.Note: This register field is sticky.660x0R/WERROR_PROT_DISABLE_CXS_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15305Error correction disable for CXS Rx path (PCIe Tx path).Note: This register field is sticky.770x0R/WERROR_PROT_DISABLE_DTIM_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15315Error correction disable for DTIM Tx path.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15323Reserved for future use.1590x00RERROR_PROT_DISABLE_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15333Global error correction disable for all Rx layers.Note: This register field is sticky.16160x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15345Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.17170x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15356Error correction disable for AXI bridge inbound request path.Note: This register field is sticky.18180x0R/WERROR_PROT_DISABLE_DMA_READPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15366Error correction disable for DMA read engine.Note: This register field is sticky.19190x0R/WERROR_PROT_DISABLE_LAYER2_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15376Error correction disable for layer 2 Rx path.Note: This register field is sticky.20200x0R/WERROR_PROT_DISABLE_LAYER3_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15386Error correction disable for layer 3 Rx path.Note: This register field is sticky.21210x0R/WERROR_PROT_DISABLE_ADM_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15396Error correction disable for ADM Rx path.Note: This register field is sticky.22220x0R/WERROR_PROT_DISABLE_CXS_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15406Error correction disable for CXS Tx path (PCIe Rx path).Note: This register field is sticky.23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15414Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFRASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr155020xCR/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFFCorrected error (1-bit ECC) counter selection and control.This is a viewport control register.Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15432Clear all correctable error counters.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15440Reserved for future use.310x0RCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15452Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15460Reserved for future use.1950x0000RCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15486Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15501Counter selection.This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFRASDP_CORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr155640x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFFCorrected error (1-bit ECC) counter data.This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseCORR_COUNTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15518Current corrected error count for the selected counter.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15525Reserved for future use.1980x000RCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15552Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15563Counter selection.Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFRASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr156550x14R/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFFUncorrected error (2-bit ECC and parity) counter selection and control.This is a viewport control register.Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseUNCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15584Clear uncorrectable errors counters.When asserted causes all counters tracking the uncorrectable errors to be cleared.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15592Reserved for future use.310x0RUNCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15604Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15612Reserved for future use.1950x0000RUNCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15638Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WUNCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15654Counter selection.This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFRASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr157180x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFFUncorrected error (2-bit ECC and parity) counter data.This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseUNCORR_COUNTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15672Current uncorrected error count for the selected counter700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15679Reserved for future use.1980x000RUNCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15706Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RUNCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15717Counter selection.Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFRASDP_ERROR_INJ_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr15798Error injection control0x1CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFFError injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occursfalsefalsefalsefalseERROR_INJ_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15736Error injection global enable.When set enables the error insertion logic.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15744Reserved for future use.310x0RERROR_INJ_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15755Error injection type: - 0: none - 1: 1-bit - 2: 2-bit540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15763Reserved for future use.760x0RERROR_INJ_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15776Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected1580x00R/WERROR_INJ_LOCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15789Error injection location.Selects where error injection takes place.You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15797Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFRASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr15905Corrected errors locations.0x20R0x00d000d0PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFFCorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15813Reserved for future use.300x0RREG_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15840Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15855Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15862Reserved for future use.19160x0RREG_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15889Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15904Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFRASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16012Uncorrected errors locations.0x24R0x00d000d0PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFFUncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15920Reserved for future use.300x0RREG_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15947Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15962Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15969Reserved for future use.19160x0RREG_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr15996Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16011Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFRASDP_ERROR_MODE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16056RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error.0x28R/W0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFFRASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them.For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16036Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error.Note: This register field is sticky.000x1R/WAUTO_LINK_DOWN_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16047Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.Note: This register field is sticky.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16055Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFRASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16084Exit RASDP error mode.0x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFFExit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16075Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16083Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFRASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16121RAM Address where a corrected error (1-bit ECC) has been detected.0x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFFRAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16103RAM Address where a corrected error (1-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16110Reserved for future use.27270x0RRAM_INDEX_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16120RAM index where a corrected error (1-bit ECC) has been detected.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFRASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16158RAM Address where an uncorrected error (2-bit ECC) has been detected.0x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFFRAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16140RAM Address where an uncorrected error (2-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16147Reserved for future use.27270x0RRAM_INDEX_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16157RAM index where an uncorrected error (2-bit ECC) has been detected.31280x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAPPF0_DLINK_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr163390x3FCRPE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAPPF DLINK Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFDATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16233This register provides capbility ID, capability version and next offset value.0x0R0x00010025PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFFData Link Feature Extended Capability Header.This register provides capbility ID, capability version and next offset value.falsefalsefalsefalseDLINK_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16189Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for Data Link Feature is 0025h.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0025RDLINK_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16206Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RDLINK_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16232Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFDATA_LINK_FEATURE_CAP_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16294This register provides description about extended feature.0x4R0x80000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFFData Link Feature Capabilities.This register provides description about extended feature.falsefalsefalsefalseSCALED_FLOW_CNTL_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16257Local Scaled Flow Control Supported.Bit 0 – Local Scaled Flow Control Supported. Bit 22:1 – RsvdP.Bits associated with features that this Port is capable of supporting are HwInit, defaulting to 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 000x1RFUTURE_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16271Local Future Data Link Feature Supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.2210x000000RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16278Reserved for future use.30230x00RDL_FEATURE_EXCHANGE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16293Data Link Feature Exchange Enable.If Set, this bit indicates that this Port will enter the DL_Feature negotiation state. Default is 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFDATA_LINK_FEATURE_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr16338This Registor privides status of the capability of data link feature.0x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFFData Link Feature Status Register.This Registor privides status of the capability of data link feature.falsefalsefalsefalseREMOTE_DATA_LINK_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16315Remote Data Link Feature SupportedFeatures Currently defined are: Bit 0 - Remote Scaled Flow Control Supported.Other Bits are undefined. Default value is 00 0000h.2200x000000RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16322Reserved for future use.30230x00RDATA_LINK_FEATURE_STATUS_VALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16337Remote Data Link Feature Supported Valid.This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature (see Section 3.2.1) and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields arefield is meaningful. This bit is Cleared on entry to state DL_Inactive.Default is 0b.31310x0RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGICPF0_PORT_LOGICPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr221800x700R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGICPort LogicregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFACK_LATENCY_TIMER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr163960x0R/W0x0c23040bPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFFAck Latency Timer and Replay Timer Register.falsefalsefalsefalseROUND_TRIP_LATENCY_TIME_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16371Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling".You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification.The limit must reflect the round trip latency from requester to completer.If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.1500x040bR/WREPLAY_TIME_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16395Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay".You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification.If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.31160x0c23R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFVENDOR_SPEC_DLLP_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr164180x4R/W0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFFVendor Specific DLLP Register.falsefalsefalsefalseVENDOR_SPEC_DLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16417Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP.Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8] = Payload (24 bits)The dllp type is in bits [7:0] while the remainder is the vendor defined payload.Note: This register field is sticky.3100xffffffffR/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPORT_FORCE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr165120x8R/W0x00800004PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PORT_FORCE_OFFPort Force Link Register.falsefalsefalsefalseLINK_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16430Link Number. Not used for endpoint. Not used for M-PCIe.Note: This register field is sticky.700x04R/WFORCED_LTSSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16443Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link).Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16451Reserved for future use.14120x0RFORCE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16470Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced Link Command field.This is a self-clearing register field. Reading from this register field always returns a "0".15150x0WLINK_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16482Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link).LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16490Reserved for future use.22220x0RDO_DESKEW_FOR_SRISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16503Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, EIEOS to Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS is set to 1.Note: This register field is sticky.23230x1R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16511Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFACK_F_ASPM_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr166390xCR/W0x1bc8c800PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFFAck Frequency and L0-L1 ASPM Control Register.falsefalsefalsefalseACK_FREQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16540Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK request for every TLP that it receives. The controller waits until the ACK Latency Timer expires, then converts the current low-priority ACK request to a high-priority ACK request and schedules the DLLP for transmission to the remote link partner. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs if the ACK Latency Timer expires, but never later.For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".Note: This register field is sticky.700x00R/WACK_N_FTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16556N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255.The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.1580xc8R/WCOMMON_CLK_N_FTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16582Common Clock N_FTS. This is the N_FTS when common clock is used.The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYThe controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 23160xc8RL0S_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16599L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 usThis field is applicable to STALL while in L0 for M-PCIe.Note: This register field is sticky.26240x3R/WL1_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16618L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 usNote: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.Note: This register field is sticky.29270x3R/WENTER_ASPMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16630ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16638Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPORT_LINK_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr168350x10R/W0x00000120PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFFPort Link Control Register.falsefalsefalsefalseVENDOR_SPECIFIC_DLLP_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16656Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.Reading from this self-clearing register field always returns a '0'.000x0R/W1CSCRAMBLE_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16665Scramble Disable. Turns off data scrambling.Note: This register field is sticky.110x0R/WLOOPBACK_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16681Loopback Enable. Turns on loopback. For more details, see "Loopback".For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration).M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.Note: This register field is sticky.220x0R/WRESET_ASSERTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16691Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).Note: This register field is sticky.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16699Reserved for future use.440x0RDLL_LINK_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16710DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit InitFC DLLPs and does not establish a link.Note: This register field is sticky.550x1R/WLINK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16719LINK_DISABLE is an internally reserved field. Do not use.Note: This register field is sticky.660x0R/WFAST_LINK_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16746Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster.The default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF register.Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'.For more details, see the "Fast Link Simulation Mode" section in the "Integrating the Controller with the PHY or Application RTL or Verification IP" chapter of the User Guide.For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).Note: This register field is sticky.770x0R/WLINK_RATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16755LINK_RATE is an internally reserved field. Do not use.Note: This register field is sticky.1180x1R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16763Reserved for future use.15120x0RLINK_CAPABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16787Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported)This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.2116R/W--23220x0rBEACON_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16796BEACON_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.24240x0R/WCORRUPT_LCRC_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16806CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WEXTENDED_SYNCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16816EXTENDED_SYNCH is an internally reserved field. Do not use.Note: This register field is sticky.26260x0R/WTRANSMIT_LANE_REVERSALE_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16826TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.27270x0R/WRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16834Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFLANE_SKEW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr169160x14R/W0x3c000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_LANE_SKEW_OFFLane Skew Register.falsefalsefalsefalseINSERT_LANE_SKEWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16848INSERT_LANE_SKEW is an internally reserved field. Do not use.Note: This register field is sticky.2300x000000R/WFLOW_CTRL_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16858Flow Control Disable. Prevents the controller from sending FC DLLPs.Note: This register field is sticky.24240x0R/WACK_NAK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16868Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs.Note: This register field is sticky.25250x0R/WELASTIC_BUFFER_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16879Selects Elasticity Buffer operating mode:0: Nominal Half Full Buffer mode1: Nominal Empty Buffer ModeNote: This register field is sticky.26260x1R/WIMPLEMENT_NUM_LANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16905Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanesThe number of lanes to be used when in Loopback Master. The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field.The controller will transition from Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field.Note: This register field is sticky.30270x7R/WDISABLE_LANE_TO_LANE_DESKEWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16915Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFTIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr170130x18R/W0x40000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFFTimer Control and Max Function Number Register.falsefalsefalsefalseMAX_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16930Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).Note: This register field is sticky.700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16938Reserved for future use.1380x00RTIMER_MOD_REPLAY_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16958Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.At Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.Note: This register field is sticky.1814R/WTIMER_MOD_ACK_NAKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16972Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.Note: This register field is sticky.23190x00R/WUPDATE_FREQ_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr16982UPDATE_FREQ_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.28240x00R/WFAST_LINK_SCALING_FACTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17004Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us)Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.*a. When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, 2ms timer is 4us and 3ms timer is 6us.Not used for M-PCIe. Note: This register field is sticky.30290x2R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17012Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFSYMBOL_TIMER_FILTER_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr171700x1CR/W0x00000140PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFFSymbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseSKP_INT_VALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17052SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP ordered sets once every 1537 symbol times.The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NBYou need to set this field again if necessary when 2K_PPM_DISABLED is changed.Note: This register field is sticky.1000x140R/WEIDLE_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17061EIDLE_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.14110x0R/WDISABLE_FC_WD_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17070Disable FC Watchdog Timer.Note: This register field is sticky.15150x0R/WMASK_RADM_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17169Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received[30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received[29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII.[28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW.[27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up[26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions[25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions[24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions[23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions[22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions[21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions[20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC[19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number.[18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR[17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native controller always passes poisoned completions to your application except when you are using the DMA read channel.[16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as URNote: This register field is sticky.31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFFILTER_MASK_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr172310x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_FILTER_MASK_2_OFFFilter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseMASK_RADM_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17230Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31:10]: Reserved[9]: CX_FLT_MASK_CPL_IN_LUT_CHECK - 0: Disable masking of checking if the tag of CPL is registered in LUT - 1: Enable masking of checking if the tag of CPL is registered in LUT[8]: CX_FLT_MASK_POIS_ERROR_REPORTING - 0: Disable masking of error reporting for Poisoned TLPs - 1: Enable masking of error reporting for Poisoned TLPs[7]: CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the SYMBOL_TIMER_FILTER_1_OFF register is set to '1'.[6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE[5]: CX_FLT_UNMASK_UR_POIS_TRGT0 - 0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination[4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass through - 1: Drop LN Messages silently[3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller Filter to handle flush request - 1: Enable controller Filter to handle flush request[2]: CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP abort for unexpected completion[1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped silently - 1: Vendor MSG Type 1 not dropped[0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0 dropped with UR error reporting - 1: Vendor MSG Type 0 not droppedNote: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr172650x24R/W0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA Multiple Outbound Decomposed NP SubRequests Control Register.falsefalsefalsefalseOB_RD_SPLIT_BURST_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17256Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to "0" disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge Ordering" in the AXI chapter of the Databook.You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device (or switch) is reordering completions that have different tags.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17264Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPL_DEBUG0_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr172780x28RPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_DEBUG0_OFFDebug Register 0falsefalsefalsefalseDEB_REG_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17277The value on cxpl_debug_info[31:0].310RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPL_DEBUG1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr172910x2CRPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_DEBUG1_OFFDebug Register 1falsefalsefalsefalseDEB_REG_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17290The value on cxpl_debug_info[63:32].310RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFTX_P_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr173450x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFFTransmit Posted FC Credit StatusfalsefalsefalsefalseTX_P_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17316Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_P_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17337Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_P_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17344Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFTX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr173990x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFFTransmit Non-Posted FC Credit StatusfalsefalsefalsefalseTX_NP_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17370Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_NP_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17391Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_NP_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17398Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFTX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr174530x38R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFFTransmit Completion FC Credit StatusfalsefalsefalsefalseTX_CPL_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17424Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_CPL_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17445Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_CPL_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17452Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFQUEUE_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr175570x3CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_QUEUE_STATUS_OFFQueue StatusfalsefalsefalsefalseRX_TLP_FC_CREDIT_NON_RETURNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17470Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.000x0RTX_RETRY_BUFFER_NEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17481Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.110x0RRX_QUEUE_NON_EMPTYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17492Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.220x0RRX_QUEUE_OVERFLOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17503Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue.330x0R/W1CRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17511Reserved for future use.1240x000RRX_SERIALIZATION_Q_NON_EMPTYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17522Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.13130x0R--15140x0rTIMER_MOD_FLOW_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17535FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the controller calculates according to the PCIe specification. For more details, see "Flow Control".Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17543Reserved for future use.30290x0RTIMER_MOD_FLOW_CONTROL_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17556FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the controller calculates according to the PCIe specification.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFVC_TX_ARBI_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr176060x40R0x0000000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFFVC Transmit Arbitration Register 1falsefalsefalsefalseWRR_WEIGHT_VC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17572WRR Weight for VC0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 700x0fRWRR_WEIGHT_VC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17583WRR Weight for VC1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 1580x00RWRR_WEIGHT_VC_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17594WRR Weight for VC2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 23160x00RWRR_WEIGHT_VC_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17605WRR Weight for VC3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFVC_TX_ARBI_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr176550x44R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFFVC Transmit Arbitration Register 2falsefalsefalsefalseWRR_WEIGHT_VC_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17621WRR Weight for VC4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 700x00RWRR_WEIGHT_VC_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17632WRR Weight for VC5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 1580x00RWRR_WEIGHT_VC_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17643WRR Weight for VC6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 23160x00RWRR_WEIGHT_VC_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17654WRR Weight for VC7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFVC0_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr177590x48R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFFSegmented-Buffer VC0 Posted Receive Queue Control.falsefalsefalsefalseVC0_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17672VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC0_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17686VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17695Reserved.Note: This register field is sticky.20200x0R/WVC0_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17704Reserved.Note: This register field is sticky.23210x1R/WVC0_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17714VC0 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17724VC0 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17733Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17745TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WVC_ORDERING_RX_QPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17758VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robinNote: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFVC0_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr178380x4CR/W0x06260060PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFFSegmented-Buffer VC0 Non-Posted Receive Queue Control.falsefalsefalsefalseVC0_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17776VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x060R/WVC0_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17790VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17799Reserved.Note: This register field is sticky.20200x0R/WVC0_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17808Reserved.Note: This register field is sticky.23210x1R/WVC0_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17818VC0 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17828VC0 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17837Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFVC0_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr179170x50R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC0 Completion Receive Queue Control.falsefalsefalsefalseVC0_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17855VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC0_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17869VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17878Reserved.Note: This register field is sticky.20200x0R/WVC0_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17887Reserved.Note: This register field is sticky.23210x1R/WVC0_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17897VC0 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC0_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17907VC0 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17916Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFVC1_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr180170x54R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC1_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17934VC1 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC1_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17948VC1 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17957Reserved.Note: This register field is sticky.20200x0R/WVC1_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17966Reserved.Note: This register field is sticky.23210x1R/WVC1_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17976VC1 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17986VC1 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr17995Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18007TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18016Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFVC1_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr180960x58R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC1_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18034VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC1_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18048VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18057Reserved.Note: This register field is sticky.20200x0R/WVC1_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18066Reserved.Note: This register field is sticky.23210x1R/WVC1_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18076VC1 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18086VC1 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18095Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFVC1_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr181750x5CR/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC1_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18113VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC1_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18127VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18136Reserved.Note: This register field is sticky.20200x0R/WVC1_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18145Reserved.Note: This register field is sticky.23210x1R/WVC1_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18155VC1 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC1_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18165VC1 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18174Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFVC2_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr182750x60R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC2_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18192VC2 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC2_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18206VC2 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18215Reserved.Note: This register field is sticky.20200x0R/WVC2_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18224Reserved.Note: This register field is sticky.23210x1R/WVC2_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18234VC2 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18244VC2 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18253Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18265TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18274Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFVC2_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr183540x64R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC2_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18292VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC2_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18306VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18315Reserved.Note: This register field is sticky.20200x0R/WVC2_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18324Reserved.Note: This register field is sticky.23210x1R/WVC2_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18334VC2 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18344VC2 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18353Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFVC2_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr184330x68R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC2_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18371VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC2_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18385VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18394Reserved.Note: This register field is sticky.20200x0R/WVC2_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18403Reserved.Note: This register field is sticky.23210x1R/WVC2_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18413VC2 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC2_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18423VC2 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18432Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFVC3_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr185330x6CR/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC3_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18450VC3 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC3_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18464VC3 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18473Reserved.Note: This register field is sticky.20200x0R/WVC3_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18482Reserved.Note: This register field is sticky.23210x1R/WVC3_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18492VC3 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18502VC3 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18511Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18523TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18532Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFVC3_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr186120x70R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC3_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18550VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC3_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18564VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18573Reserved.Note: This register field is sticky.20200x0R/WVC3_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18582Reserved.Note: This register field is sticky.23210x1R/WVC3_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18592VC3 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18602VC3 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18611Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFVC3_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr186910x74R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC3_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18629VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC3_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18643VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18652Reserved.Note: This register field is sticky.20200x0R/WVC3_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18661Reserved.Note: This register field is sticky.23210x1R/WVC3_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18671VC3 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC3_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18681VC3 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18690Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFGEN2_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr18975Link Width and Speed Change Control Register.0x10CR/W0x000108c8PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN2_CTRL_OFFThis register is used to control various functions of the controller related to link training, lane reversal, and equalization.falsefalsefalsefalseFAST_TRAINING_SEQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18718Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.700xc8R/WNUM_OF_LANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18758Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - ..When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.1280x08R/WPRE_DET_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18808Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.Note: This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.15130x0R/WfalsetruefalseLANE00x0Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detectedLANE10x1Connect logical Lane0 to physical lane 1LANE150x4Connect logical Lane0 to physical lane 15LANE30x2Connect logical Lane0 to physical lane 3LANE70x3connect logical lane0 to physical lane 7AUTO_LANE_FLIP_CTRL_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18826Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.16160x1R/WDIRECT_SPEED_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18859Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed.When the speed change occurs, the controller will clear the contents of this field; and a read to this field by your software will return a "0".To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this fieldIf you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the controller clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 17170x0R/WCONFIG_PHY_TX_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18876Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low SwingThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.18180x0R/WCONFIG_TX_COMP_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18891Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1").This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WSEL_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18907Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dBThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.20200x0R/WGEN1_EI_INFERENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18925Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical IdleNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18933Reserved for future use.23220x0RLANE_UNDER_TESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18949The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.27240x0R/W--29280x0rFORCE_LANE_FLIPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18966Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18974Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPHY_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr189990x110RPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_STATUS_OFFPHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.falsefalsefalsefalsePHY_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr18998PHY Status. Data received directly from the phy_cfg_status bus.These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband status signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.310RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPHY_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr190210x114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_CONTROL_OFFPHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.falsefalsefalsefalsePHY_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19020PHY Control. Data sent directly to the cfg_phy_control bus.These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband control signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFTRGT_MAP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr190800x11CR/W0x0000006fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFFProgrammable Target Map Control Register.falsefalsefalsefalseTARGET_MAP_PFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19034Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.500x2fR/WTARGET_MAP_ROMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19045Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.660x1R/W--1270x0rTARGET_MAP_RESERVED_13_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19057Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) 15130x0RTARGET_MAP_INDEXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19067The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits.20160x00R/WTARGET_MAP_RESERVED_21_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19079Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) 31210x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFMSI_CTRL_ADDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr191000x120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFFIntegrated MSI Reception Module (iMRM) Address Register.falsefalsefalsefalseMSI_CTRL_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19099Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination.Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and also to see if it satisfies the definition of an MSI interrupt request. When these conditions are satisfied the Memory Write request is marked as an MSI request.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFMSI_CTRL_UPPER_ADDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr191160x124R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFFIntegrated MSI Reception Module Upper Address Register.falsefalsefalsefalseMSI_CTRL_UPPER_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19115Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFMSI_CTRL_INT_0_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr191330x128R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_0_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19132MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFMSI_CTRL_INT_0_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr191510x12CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_0_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19150MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFMSI_CTRL_INT_0_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr191690x130R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_0_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19168MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFMSI_CTRL_INT_1_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr191860x134R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_1_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19185MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFMSI_CTRL_INT_1_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr192040x138R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_1_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19203MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFMSI_CTRL_INT_1_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr192220x13CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_1_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19221MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFMSI_CTRL_INT_2_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr192390x140R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_2_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19238MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFMSI_CTRL_INT_2_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr192570x144R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_2_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19256MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFMSI_CTRL_INT_2_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr192750x148R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_2_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19274MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFMSI_CTRL_INT_3_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr192920x14CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_3_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19291MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFMSI_CTRL_INT_3_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr193100x150R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_3_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19309MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFMSI_CTRL_INT_3_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr193280x154R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_3_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19327MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFMSI_CTRL_INT_4_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr193450x158R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_4_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19344MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFMSI_CTRL_INT_4_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr193630x15CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_4_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19362MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFMSI_CTRL_INT_4_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr193810x160R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_4_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19380MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFMSI_CTRL_INT_5_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr193980x164R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_5_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19397MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFMSI_CTRL_INT_5_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr194160x168R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_5_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19415MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFMSI_CTRL_INT_5_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr194340x16CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_5_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19433MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFMSI_CTRL_INT_6_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr194510x170R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_6_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19450MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFMSI_CTRL_INT_6_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr194690x174R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_6_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19468MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFMSI_CTRL_INT_6_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr194870x178R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_6_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19486MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFMSI_CTRL_INT_7_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr195040x17CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_7_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19503MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFMSI_CTRL_INT_7_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr195220x180R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_7_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19521MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFMSI_CTRL_INT_7_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr195400x184R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_7_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19539MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFMSI_GPIO_IO_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr195540x188R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_GPIO_IO_OFFIntegrated MSI Reception Module General Purpose IO Register.falsefalsefalsefalseMSI_GPIO_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19553MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0]Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFCLOCK_GATING_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr196220x18CR/W0x00000003PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFFThis register enables you to disable dynamic clock gating. By default dynamic clock gating is on, allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module, DWC_pcie_clk_rst.v, and is initiated by the controllers clock enable signals. The following modules support dynamic clock gating: - AXI Bridge - RADMfalsefalsefalsefalseRADM_CLK_GATING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19586RADM Clock Gating Enable. This register, if set, enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock, radm_clk_g, to the RADM and is enabled when the controllers clock enable signal, en_radm_clk_g, is asserted. The RADM clock is a gated version of the controller clock, core_clk. The controller de-asserts en_radm_clk_g when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. - 0: Disable - 1: Enable (default)Note: This register field is sticky.000x1R/WAXI_CLK_GATING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19613AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock, the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock, mstr_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, mstr_aclk_active, is asserted. For the AXI Slave this module provides the gated clock, slv_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, slv_aclk_active, is asserted. If the AXI DBI Slave is enabled (DBI_4SLAVE_POPULATED=1) the module provides the gated clock, dbi_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, dbi_aclk_active, is asserted. The controller de-asserts the clock enable signals when the respective AXI Master/Slave interfaces are idle. - 0: Disable - 1: Enable (default)Note: This register field is sticky.110x1R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19621Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFGEN3_RELATED_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr199670x190R/W0x00402001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_RELATED_OFFGen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_ZRXDC_NONCOMPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19657Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rates.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19665Reserved for future use.710x00RDISABLE_SCRAMBLER_GEN_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19680Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY).Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.880x0R/WEQ_PHASE_2_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19701Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.990x0R/WEQ_EIEOS_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19715Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.10100x0R/WEQ_REDOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19735Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is infinite or you do not want eq requests and redo, setting this bit to 1 will stop the EQ requests and EQ redo so that the link can go ahead to L0 state for packet trasmissions.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.11110x0R/WRXEQ_PH01_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19766Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.12120x0R/WRXEQ_RGRDLESS_RXTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19792When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.13130x1R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19800Reserved for future use.15140x0RGEN3_EQUALIZATION_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19814Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.16160x0R/WGEN3_DLLP_XMT_DELAY_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19828DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.17170x0R/WGEN3_DC_BALANCE_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19840DC Balance Disable. Disable DC Balance feature.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.18180x0R/WRSVDP_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19848Reserved for future use.20190x0RAUTO_EQ_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19875Autonomous Equalization Disable. When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.21210x0R/WUSP_SEND_8GT_EQ_TS2_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19902Upstream Port Send 8GT/s or 16GT/s EQ TS2 Disable. The base spec defines that USP can optionally send 8GT or 16GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 or Gen5 Data Rate. If this register set to 0, USP sends 8GT or 16GT EQ TS2. If this register set to 1, USP does not send 8GT or 16GT EQ TS2. This applies to upstream ports only. No Function for downstream ports.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. Value after reset in Gen4/Gen5 is 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.22220x1R/WGEN3_EQ_INVREQ_EVAL_DIFF_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19917Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.23230x0R/WRATE_SHADOW_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19958Rate Shadow Select. This register value decide the Data Rate of shadow register. - 00b: Gen3 Data Rate is selected for shadow register. - 01b: Gen4 Data Rate is selected for shadow register. - 10b: Gen5 Data Rate is selected for shadow register. - 11b: Reserved.The following shadow registers are controlled by this register. - GEN3_RELATED_OFF[9] EQ_PHASE_2_3 - GEN3_RELATED_OFF[12] RXEQ_PH01_EN - GEN3_RELATED_OFF[19] RE_EQ_REQUEST_ENABLE - GEN3_RELATED_OFF[21] AUTO_EQ_DISABLE - GEN3_RELATED_OFF[22] USP_SEND_8GT_EQ_TS2_DISABLE - GEN3_EQ_LOCAL_FS_LF_OFF[5:0] GEN3_EQ_LOCAL_LF - GEN3_EQ_LOCAL_FS_LF_OFF[11:6] GEN3_EQ_LOCAL_FS - GEN3_EQ_PSET_COEFF_MAP_0[5:0] GEN3_EQ_PRE_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[11:6] GEN3_EQ_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[17:12] GEN3_EQ_POSET_CURSOR_PSET - GEN3_EQ_CONTROL_OFF[3:0] GEN3_EQ_FB_MODE - GEN3_EQ_CONTROL_OFF[4] GEN3_EQ_PHASE23_EXIT_MODE - GEN3_EQ_CONTROL_OFF[5] GEN3_EQ_EVAL_2MS_DISABLE - GEN3_EQ_CONTROL_OFF[23:8] GEN3_EQ_PSET_REQ_VEC - GEN3_EQ_CONTROL_OFF[24] GEN3_EQ_FOM_INC_INITIAL_EVAL - GEN3_EQ_CONTROL_OFF[25] GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[4:0] GEN3_EQ_FMDC_T_MIN_PHASE23 - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[9:5] GEN3_EQ_FMDC_N_EVALS - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[13:10] GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[17:14] GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTANote: This register field is sticky.25240x0R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19966Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFGEN3_EQ_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr201990x1A8R/W0x05039f71PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFFGen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_EQ_FB_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr19995Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: ReservedNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.300x1R/WGEN3_EQ_PHASE23_EXIT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20042Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2"For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLockWhen optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2"Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.440x1R/WGEN3_EQ_EVAL_2MS_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20066Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.550x1R/WGEN3_LOWER_RATE_EQ_REDO_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20080Support EQ redo and lower rate change: - 0: not support - 1: supportNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.660x1R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20088Reserved for future use.770x0RGEN3_EQ_PSET_REQ_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20143Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: ReservedNote: You must contact your PHY vendor to ensure 24 ms timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.2380x039fR/WGEN3_EQ_FOM_INC_INITIAL_EVALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20163Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: IncludeNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.24240x1R/WGEN3_EQ_PSET_REQ_AS_COEFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20174GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WGEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20190Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: requestNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.26260x1R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20198Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr203050x1ACR/W0x00000040PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes.falsefalsefalsefalseGEN3_EQ_FMDC_T_MIN_PHASE23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20230Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients.Allowed values 0,1,...,24.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.400x00R/WGEN3_EQ_FMDC_N_EVALSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20257Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found.Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH.When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.950x02R/WGEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20277Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth.Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.13100x0R/WGEN3_EQ_FMDC_MAX_POST_CUSROR_DELTAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20296Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.17140x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20304Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFORDER_RULE_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr203390x1B4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFFOrder Rule Control Register.falsefalsefalsefalseNP_PASS_PPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20319Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P700x00R/WCPL_PASS_PPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20330Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P1580x00R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20338Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPIPE_LOOPBACK_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr203950x1B8R/W0x000000ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFFPIPE Loopback Control Register.falsefalsefalsefalseLPBK_RXVALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20351LPBK_RXVALID is an internally reserved field. Do not use.Note: This register field is sticky.1500x00ffR/WRXSTATUS_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20360RXSTATUS_LANE is an internally reserved field. Do not use.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20368Reserved for future use.23220x0RRXSTATUS_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20377RXSTATUS_VALUE is an internally reserved field. Do not use.2624WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20385Reserved for future use.30270x0RPIPE_LOOPBACKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20394PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFMISC_CONTROL_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr205890x1BCR/W0x0007ff48PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MISC_CONTROL_1_OFFDBI Read-Only Write Enable Register.falsefalsefalsefalseDBI_RO_WR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20413Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'.For more details, see "Writing to Read-Only Registers" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.000x0R/WDEFAULT_TARGETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20434Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status is generated for non-posted requests. - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application.For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.110x0R/WUR_CA_MASK_4_TRGT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20448When this field is set to '1', the controller suppresses error logging, error message generation, and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is, when DEFAULT_TARGET =1). For more details, see "Advanced Error Handling For Received TLPs" chapter of the Databook.Note: This register field is sticky.220x0R/WSIMPLIFIED_REPLAY_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20467Enables Simplified Replay Timer (Gen4). For more details, see "Transmit Replay" in "Transmit TLP Processing" section in the "Controller Operations" chapter of the Databook.Simplified Replay Timer can have the following Values: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b.The Simplified Replay Timer value must not be changed while the link is in use.Note: This register field is sticky.330x1R/WDISABLE_AUTO_LTR_CLR_MSGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20485Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear message.For more details, see "Latency Tolerance Reporting (LTR) Message Generation[EP Mode]" in "Message Generation" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.440x0R/WARI_DEVICE_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20495When ARI is enabled, this field enables use of the device ID.Note: This register field is sticky.550x0R/WCPLQ_MNG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20505This field enables the Completion Queue Management feature.Note: This register field is sticky.660x1R/WCFG_TLP_BYPASS_EN_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20524Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG - 1: Configuration TLPs are routed according to the setting of CONFIG_LIMIT_REGNote: When app_req_retry_en is asserted, the setting of this field is ignored.Note: This register field is sticky.770x0R/WCONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20545Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of TARGET_ABOVE_CONFIG_LIMIT_REG field.Your application must set a proper value for this field based on your extended configuration registers. For more details, see the "CDM/ELBI Register Space Access Through CFG Request" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.1780x3ffR/WTARGET_ABOVE_CONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20558Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1Note: This register field is sticky.19180x1R/WP2P_TRACK_CPL_TO_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20569Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reportingNote: This register field is sticky.20200x0R/WP2P_ERR_RPT_CTRLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20580Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completionNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20588Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFMULTI_LANE_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr206630x1C0R/W0x00000080PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFFUpConfigure Multi-lane Control Register.Used when upsizing or downsizing the link width through Configuration state without bringing the link down.For more details, see the "Link Establishment" section in the "ControllerOperations" chapter of the Databook.falsefalsefalsefalseTARGET_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20616Target Link Width.Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32This field is reserved (fixed to '0') for M-PCIe.500x00R/WDIRECT_LINK_WIDTH_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20639Directed Link Width Change.The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure or autonomous width downsizing in the Configuration state.The controller self-clears this field when the controller accepts this request.This field is reserved (fixed to '0') for M-PCIe.660x0R/WUPCONFIGURE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20654Upconfigure Support.The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.770x1R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20662Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPHY_INTEROP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr207790x1C4R/W0x00000a44PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFFPHY Interoperability Control Register.falsefalsefalsefalseRXSTANDBY_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20692Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus HandshakeThis field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.600x44R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20700Reserved for future use.770x0RL1SUB_EXIT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20717L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. - 0: Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1.Note: This register field is sticky.880x0R/WL1_NOWAIT_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20738L1 entry control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Controller waits for the PHY to acknowledge transition to P1 before entering L1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.990x1RL1_CLK_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20755L1 Clock control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1.Note: This register field is sticky.10100x0R/WP2NOBEACON_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20770P2.NoBeacon Enable bit. - 1: Controller drives P2.NoBeacon encoding for PHY power down state, when the link goes to L2. - 0: Controller drives P2 encoding for PHY power down state, when the link goes to L2.Note:This field is reserved (fixed to '0') if CX_P2NOBEACON_ENABLE is not set.Note: This register field is sticky.11110x1R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20778Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr208150x1C8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason.Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire.falsefalsefalsefalseLOOK_UP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20801This number selects one entry to delete of the TRGT_CPL_LUT.3000x00000000R/WDELETE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20814This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field.This is a self-clearing register field. Reading from this register field always returns a '0'.31310x0WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFLINK_FLUSH_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr208610x1CCR/W0xff000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFFLink Reset Request Flush Control Register.falsefalsefalsefalseAUTO_FLUSH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20843Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge.The flushing process is initiated if any of the following events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset.If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the Databook.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20851Reserved for future use.2310x000000RRSVD_I_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20860This is an internally reserved field. Do not use.Note: This register field is sticky.31240xffR/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFAMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr20991AXI Bridge Slave Error Response Register.0x1D0R/W0x00009c00PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFFAXI Bridge Slave Error Response Register.falsefalsefalsefalseAMBA_ERROR_RESPONSE_GLOBALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20890Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data for non-posted requests) and ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and look at bit [2] for other scenarios.AXI: - 0: OKAY (with FFFF data for non-posted requests) - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)The error response mapping is not applicable to Non-existent Vendor ID register reads.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20898Reserved for future use.110x0RAMBA_ERROR_RESPONSE_VENDORIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20917Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data). The controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERRORAXI: - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.220x0R/WAMBA_ERROR_RESPONSE_CRSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20939CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - always returns OKAYAXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20947Reserved for future use.950x00RAMBA_ERROR_RESPONSE_MAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20982AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request) -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) -> DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR -- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERRThe AXI bridge internally drops (processes internally but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave interface.The controller sets the AXI slave read databus to 0xFFFF for all error responses.Note: This register field is sticky.15100x27R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr20990Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFAMBA_LINK_TIMEOUT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr210380x1D4R/W0x00000032PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFFLink Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a "flush" timer. The timeout value of the timer is set by this register. If the timer times out before the PCIe link is operational, the bridge TX request queues are flushed. For more details, see the "AXI Bridge Initialization, Clocking and Reset" section in the AXI chapter of the Databook.falsefalsefalsefalseLINK_TIMEOUT_PERIOD_DEFAULTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21019Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests.The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is 4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between 16% and 17%.Note: This register field is sticky.700x32R/WLINK_TIMEOUT_ENABLE_DEFAULTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21029Disable Flush. You can disable the flush feature by setting this field to "1".Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21037Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFAMBA_ORDERING_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr211480x1D8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFFAMBA Ordering Control.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21049Reserved for future use.000x0RAX_SNP_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21063AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted Requests" section in the AXI chapter of the Databook.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21071Reserved for future use.220x0RAX_MSTR_ORDR_P_EVENT_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21115AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, "NP must not pass P" at the AXI Master Interface.The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination. It does this by waiting for the all of the write responses on the B channel. This can affect the performance of the master read channel.For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave. - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. - 11: ReservedNote 2: This setting will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP write transactions which are always serialized with P write transactions.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21123Reserved for future use.650x0RAX_MSTR_ZEROLREAD_FWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21139AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is forward to the application.770x0R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21147Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFCOHERENCY_CONTROL_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr211850x1E0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFFACE Cache Coherency Control Register 1falsefalsefalsefalseCFG_MEMTYPE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21162Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = PeripheralNote: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21170Reserved for future use.110x0RCFG_MEMTYPE_BOUNDARY_LOW_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21184Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are in the lower address space region; addresses equal or greater than this value are in the upper address space region.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFCOHERENCY_CONTROL_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr212000x1E4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFFACE Cache Coherency Control Register 2falsefalsefalsefalseCFG_MEMTYPE_BOUNDARY_HIGH_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21199Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFCOHERENCY_CONTROL_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr212580x1E8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFFACE Cache Coherency Control Register 3falsefalsefalsefalse--200x0rCFG_MSTR_ARCACHE_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21216Master Read CACHE Signal Behavior.Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE fieldNote: This register field is sticky.630x0R/W--1070x0rCFG_MSTR_AWCACHE_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21232Master Write CACHE Signal Behavior.Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE fieldNote: for message requests the value of mstr_awcache is always "0000" regardless of the value of this bitNote: This register field is sticky.14110x0R/W--18150x0rCFG_MSTR_ARCACHE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21243Master Read CACHE Signal Value.Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'.Note: This register field is sticky.22190x0R/W--26230x0rCFG_MSTR_AWCACHE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21257Master Write CACHE Signal Value.Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'.Note: not applicable to message requests; for message requests the value of mstr_awcache is always "0000"Note: This register field is sticky.30270x0R/W--31310x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFAXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr212910x1F0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFFLower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_LOW_RESERVEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21280Reserved for future use.Note: This register field is sticky.1100x000RCFG_AXIMSTR_MSG_ADDR_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21290Lower 20 bits of the programmable AXI address for Messages.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFAXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr213060x1F4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFFUpper 32 bits of the programmable AXI address where Messages coming from wire are mapped to.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21305Upper 32 bits of the programmable AXI address for Messages.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPCIE_VERSION_NUMBER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr213310x1F8R0x3533302aPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFFPCIe Controller IIP Release Version Number. The version number is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21330Version Number.3100x3533302aRregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPCIE_VERSION_TYPE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr213560x1FCR0x6c703038PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFFPCIe Controller IIP Release Version Type. The type is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21355Version Type.3100x6c703038RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFMSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr213980x240R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFFMSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21378MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present.Note: This register field is sticky.000x0R/WMSIX_ADDRESS_MATCH_RESERVED_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21388Reserved.Note: This register field is sticky.110x0RMSIX_ADDRESS_MATCH_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21397MSI-X Address Match Low Address.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFMSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr214200x244R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFFMSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21419MSI-X Address Match High Address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFMSIX_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr214940x248W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_DOORBELL_OFFMSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. - For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF, the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.falsefalsefalsefalseMSIX_DOORBELL_VECTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21445MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.1000x000WMSIX_DOORBELL_RESERVED_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21452Reserved.11110x0WMSIX_DOORBELL_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21461MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with.14120x0WMSIX_DOORBELL_VF_ACTIVEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21470MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction.15150x0WMSIX_DOORBELL_VFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21478MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.23160x00WMSIX_DOORBELL_PFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21486MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction.28240x00WMSIX_DOORBELL_RESERVED_29_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21493Reserved.31290x0WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFMSIX_RAM_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr216320x24CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFFMSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook.falsefalsefalsefalseMSIX_RAM_CTRL_TABLE_DSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21512MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode.Note: This register field is sticky.000x0R/WMSIX_RAM_CTRL_TABLE_SDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21523MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode.Note: This register field is sticky.110x0R/WMSIX_RAM_CTRL_RESERVED_2_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21533Reserved.Note: This register field is sticky.720x00RMSIX_RAM_CTRL_PBA_DSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21544MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode.Note: This register field is sticky.880x0R/WMSIX_RAM_CTRL_PBA_SDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21555MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode.Note: This register field is sticky.990x0R/WMSIX_RAM_CTRL_RESERVED_10_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21565Reserved.Note: This register field is sticky.15100x00RMSIX_RAM_CTRL_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21581MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power signals for both RAMs.It is up to the application to ensure the RAMs are in the proper power state before trying to access them. Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality.Note: This register field is sticky.16160x0R/WMSIX_RAM_CTRL_RESERVED_17_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21591Reserved.Note: This register field is sticky.23170x00RMSIX_RAM_CTRL_DBG_TABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21606MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.24240x0R/WMSIX_RAM_CTRL_DBG_PBAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21621MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.25250x0R/WMSIX_RAM_CTRL_RESERVED_26_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21631Reserved.Note: This register field is sticky.31260x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPL_LTR_LATENCY_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr217260x430R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFFLTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.falsefalsefalsefalseSNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21654Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 900x000R/WSNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21665Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 12100x0R/WRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21673Reserved for future use.14130x0RSNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21684Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 15150x0R/WNO_SNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21695No Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25160x000R/WNO_SNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21706No Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28260x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21714Reserved for future use.30290x0RNO_SNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21725No Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFAUX_CLK_FREQ_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr217610x440R/W0x00000018PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFFAuxiliary Clock Frequency Control Register.falsefalsefalsefalseAUX_CLK_FREQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21752The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted.If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).Note: This register field is sticky.900x018R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21760Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFL1_SUBSTATES_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr218210x444R/W0x000000d2PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_L1_SUBSTATES_OFFL1 Substates Timing Register.falsefalsefalsefalseL1SUB_T_POWER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21774Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3.Note: This register field is sticky.100x2R/WL1SUB_T_L1_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21784Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15.Note: This register field is sticky.520x4R/WL1SUB_T_PCLKACKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21797Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be L1SUB_T_PCLKACK + 1. Range is 0..3Note: This register field is sticky.760x3R/WL1SUB_LOW_POWER_CLOCK_SWITCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21812If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the controller will delay the switching of aux_clk to the slow platform clock until it detects that the link partner has de-asserted CLKREQ#.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21820Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPOWERDOWN_CTRL_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr218820x448R/W0x00000220PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFFPowerdown Control and Status Register.falsefalsefalsefalsePOWERDOWN_FORCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21840This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event that the P2 Powerdown transition does not complete. It will allow the controller to proceed with the transition to the P1 Powerdown state. This field always reads back as 1'b0.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21848Reserved for future use.310x0RPOWERDOWN_MAC_POWERDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21859This field represents the Powerdown value driven by the controller to the PHY.740x2RPOWERDOWN_PHY_POWERDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21873This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller, when the PHY has returned the Phystatus acknowledgment for the Powerdown transition.1180x2RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21881Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFGEN4_LANE_MARGINING_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr219700x480R/W0x05201409PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFFGen4 Lane Margining 1 Register.falsefalsefalsefalseMARGINING_NUM_TIMING_STEPSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21898M(NumTimingSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.500x09R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21906Reserved for future use.760x0RMARGINING_MAX_TIMING_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21919M(MaxTimingOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.1380x14R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21927Reserved for future use.15140x0RMARGINING_NUM_VOLTAGE_STEPSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21940M(NumVoltageSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.22160x20R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21948Reserved for future use.23230x0RMARGINING_MAX_VOLTAGE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21961M(MaxVoltageOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.29240x05R/WRSVDP_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21969Reserved for future use.31300x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFGEN4_LANE_MARGINING_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr221170x484R/W0x060f0000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFFGen4 Lane Margining 2 Register.falsefalsefalsefalseMARGINING_SAMPLE_RATE_VOLTAGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21989M(SamplingRateVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateVoltage) is fixed to 63 internally.Note: This register field is sticky.500x00R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr21997Reserved for future use.760x0RMARGINING_SAMPLE_RATE_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22013M(SamplingRateTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter , see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateTiming) is fixed to 63 internally.Note: This register field is sticky.1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22021Reserved for future use.15140x0RMARGINING_MAXLANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22034M(MaxLanes) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.20160x0fR/WRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22042Reserved for future use.23210x0RMARGINING_VOLTAGE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22055M(VoltageSupported) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.24240x0R/WMARGINING_IND_UP_DOWN_VOLTAGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22068M(IndUpDownVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.25250x1R/WMARGINING_IND_LEFT_RIGHT_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22081M(IndLeftRightTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.26260x1R/WMARGINING_SAMPLE_REPORTING_METHODPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22095M(SampleReportingMethod) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.27270x0R/WMARGINING_IND_ERROR_SAMPLERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22108M(IndErrorSampler) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22116Reserved for future use.30290x0R--31310x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPIPE_RELATED_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr221790x490R/W0x00000022PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PIPE_RELATED_OFFPIPE Related Register.This register controls the pipe's capabitity, control, and status parameters.falsefalsefalsefalseRX_MESSAGE_BUS_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22137RXMessageBusWriteBufferDepth defined in the PIPE Specification.Indicates the number of write buffer entries that the PHY has implemented to receive writes from the controller.If the value is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the controller issues only write_commited commands, never write_uncommitted.Note: This register field is sticky.300x2R/WTX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22151TXMessageBusMinWriteBufferDepth defined in the PIPE Specification.Indicates the minimum number of write buffer entries that the PHY expects the controller to implement to receive writes from it.Note: This register field is sticky.740x2RPIPE_GARBAGE_DATA_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22170PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set until when any of the following three conditions are true: -- RxValid is deasserted -- a valid RxStartBlock is received at 128b/130b encoding -- a valid COM symbol is received at 8b/10b encodingNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22178Reserved for future use.3190x000000RmemoryPE0_DWC_pcie_ctl.AXI_Slave.PF0_PCIE_CAP_DBI2PF0_PCIE_CAP_DBI2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr221860x1000700xFR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DBI2DBI2 Shadow Block: PF PCI Express Capability StructuregroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2PF0_MSIX_CAP_DBI2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr223180x1000B0RPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2DBI2 Shadow Block: PF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGSHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr222310x0R0x00800000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22205Reserved for future use.1500x0000RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22221MSI-X Table Size in the shadow register.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22230Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGSHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr222740x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22255MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22273MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGSHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr223170x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22298MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22316MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2PF0_TPH_CAP_DBI2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr224740x100208RPE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_DBI2DBI2 Shadow Block: PF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGSHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr224730x4R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REGShadow register TPH Requestor Capability Register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22338No ST Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22356Interrupt Vector Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22374Device Specific Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22383Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22401Extended TPH Requester Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22419ST Table Location Bit 0 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22437ST Table Location Bit 1 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22446Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22463ST Table Size in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22472Reserved for future use.31270x00RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAPPF0_ATU_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr482710x300000R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAPATU Por Logic StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr225810x0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22492When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22503When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22512This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22523When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22535When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22547Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22560When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22580Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr227890x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22602MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22614TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22634TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22646TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22659Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22671Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22694TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22711Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22732Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22746DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22766CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22778Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22788Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr228260x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22814Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22825Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr228420xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22841Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr228690x10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22858Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22868Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr228980x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22897When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr229120x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22911Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr229440x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22931Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22943Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr230570x100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22958When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22971When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22984When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr22997When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23010When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23022Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23036When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23056Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr233520x104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23082MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23107BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23125Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23136TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23147TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23159ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23172TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23186Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23205Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23218PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23234Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23250Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23269Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23284CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23296Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23341Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23351Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr233890x108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23377Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23388Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr234030x10CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23402Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr234300x110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23419Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23429Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr234690x114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23455Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23468Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr234850x118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23484Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr235170x120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23504Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23516Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr236200x200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23531When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23542When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23551This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23562When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23574When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23586Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23599When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23619Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr238280x204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23641MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23653TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23673TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23685TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23698Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23710Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23733TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23750Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23771Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23785DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23805CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23817Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23827Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr238650x208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23853Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23864Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr238810x20CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23880Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr239080x210R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23897Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23907Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr239370x214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23936When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr239510x218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23950Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr239830x220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23970Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23982Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr240960x300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr23997When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24010When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24023When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24036When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24049When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24061Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24075When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24095Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr243910x304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24121MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24146BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24164Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24175TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24186TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24198ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24211TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24225Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24244Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24257PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24273Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24289Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24308Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24323CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24335Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24380Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24390Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr244280x308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24416Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24427Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr244420x30CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24441Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr244690x310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24458Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24468Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr245080x314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24494Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24507Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr245240x318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24523Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr245560x320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24543Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24555Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr246590x400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24570When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24581When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24590This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24601When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24613When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24625Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24638When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24658Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr248670x404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24680MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24692TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24712TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24724TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24737Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24749Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24772TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24789Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24810Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24824DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24844CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24856Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24866Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr249040x408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24892Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24903Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr249200x40CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24919Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr249470x410R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24936Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24946Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr249760x414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24975When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr249900x418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr24989Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr250220x420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25009Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25021Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr251350x500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25036When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25049When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25062When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25075When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25088When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25100Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25114When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25134Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr254300x504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25160MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25185BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25203Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25214TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25225TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25237ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25250TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25264Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25283Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25296PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25312Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25328Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25347Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25362CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25374Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25419Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25429Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr254670x508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25455Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25466Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr254810x50CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25480Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr255080x510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25497Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25507Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr255470x514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25533Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25546Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr255630x518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25562Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr255950x520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25582Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25594Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr256980x600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25609When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25620When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25629This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25640When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25652When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25664Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25677When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25697Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr259060x604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25719MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25731TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25751TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25763TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25776Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25788Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25811TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25828Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25849Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25863DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25883CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25895Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25905Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr259430x608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25931Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25942Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr259590x60CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25958Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr259860x610R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25975Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr25985Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr260150x614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26014When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr260290x618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26028Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr260610x620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26048Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26060Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr261740x700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26075When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26088When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26101When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26114When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26127When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26139Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26153When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26173Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr264690x704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26199MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26224BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26242Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26253TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26264TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26276ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26289TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26303Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26322Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26335PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26351Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26367Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26386Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26401CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26413Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26458Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26468Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr265060x708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26494Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26505Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr265200x70CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26519Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr265470x710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26536Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26546Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr265860x714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26572Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26585Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr266020x718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26601Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr266340x720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26621Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26633Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr267370x800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26648When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26659When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26668This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26679When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26691When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26703Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26716When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26736Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr269450x804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26758MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26770TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26790TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26802TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26815Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26827Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26850TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26867Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26888Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26902DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26922CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26934Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26944Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr269820x808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26970Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26981Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr269980x80CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr26997Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr270250x810R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27014Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27024Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr270540x814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27053When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr270680x818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27067Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr271000x820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27087Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27099Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr272130x900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27114When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27127When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27140When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27153When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27166When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27178Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27192When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27212Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr275080x904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27238MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27263BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27281Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27292TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27303TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27315ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27328TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27342Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27361Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27374PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27390Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27406Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27425Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27440CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27452Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27497Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27507Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr275450x908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27533Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27544Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr275590x90CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27558Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr275860x910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27575Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27585Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr276250x914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27611Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27624Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr276410x918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27640Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr276730x920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27660Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27672Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr277760xA00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27687When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27698When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27707This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27718When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27730When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27742Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27755When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27775Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr279840xA04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27797MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27809TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27829TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27841TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27854Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27866Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27889TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27906Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27927Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27941DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27961CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27973Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr27983Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr280210xA08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28009Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28020Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr280370xA0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28036Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr280640xA10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28053Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28063Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr280930xA14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28092When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr281070xA18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28106Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr281390xA20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28126Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28138Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr282520xB00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28153When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28166When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28179When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28192When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28205When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28217Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28231When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28251Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr285470xB04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28277MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28302BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28320Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28331TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28342TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28354ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28367TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28381Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28400Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28413PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28429Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28445Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28464Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28479CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28491Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28536Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28546Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr285840xB08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28572Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28583Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr285980xB0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28597Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr286250xB10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28614Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28624Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr286640xB14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28650Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28663Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr286800xB18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28679Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr287120xB20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28699Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28711Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr288150xC00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28726When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28737When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28746This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28757When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28769When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28781Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28794When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28814Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr290230xC04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28836MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28848TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28868TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28880TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28893Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28905Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28928TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28945Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28966Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr28980DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29000CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29012Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29022Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr290600xC08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29048Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29059Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr290760xC0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29075Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr291030xC10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29092Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29102Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr291320xC14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29131When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr291460xC18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29145Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr291780xC20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29165Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29177Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr292910xD00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29192When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29205When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29218When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29231When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29244When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29256Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29270When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29290Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr295860xD04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29316MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29341BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29359Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29370TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29381TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29393ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29406TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29420Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29439Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29452PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29468Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29484Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29503Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29518CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29530Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29575Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29585Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr296230xD08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29611Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29622Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr296370xD0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29636Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr296640xD10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29653Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29663Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr297030xD14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29689Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29702Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr297190xD18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29718Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr297510xD20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29738Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29750Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr298540xE00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29765When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29776When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29785This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29796When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29808When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29820Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29833When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29853Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr300620xE04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29875MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29887TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29907TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29919TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29932Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29944Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29967TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr29984Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30005Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30019DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30039CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30051Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30061Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr300990xE08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30087Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30098Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr301150xE0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30114Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr301420xE10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30131Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30141Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr301710xE14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30170When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr301850xE18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30184Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr302170xE20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30204Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30216Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr303300xF00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30231When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30244When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30257When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30270When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30283When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30295Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30309When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30329Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr306250xF04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30355MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30380BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30398Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30409TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30420TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30432ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30445TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30459Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30478Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30491PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30507Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30523Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30542Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30557CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30569Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30614Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30624Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr306620xF08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30650Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30661Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr306760xF0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30675Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr307030xF10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30692Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30702Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr307420xF14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30728Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30741Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr307580xF18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30757Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr307900xF20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30777Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30789Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr308930x1000R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30804When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30815When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30824This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30835When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30847When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30859Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30872When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30892Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr311010x1004R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30914MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30926TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30946TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30958TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30971Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr30983Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31006TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31023Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31044Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31058DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31078CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31090Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31100Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr311380x1008R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31126Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31137Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr311540x100CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31153Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr311810x1010R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31170Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31180Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr312100x1014R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31209When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr312240x1018R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31223Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr312560x1020R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31243Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31255Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr313690x1100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31270When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31283When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31296When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31309When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31322When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31334Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31348When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31368Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr316640x1104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31394MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31419BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31437Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31448TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31459TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31471ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31484TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31498Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31517Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31530PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31546Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31562Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31581Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31596CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31608Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31653Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31663Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr317010x1108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31689Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31700Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr317150x110CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31714Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr317420x1110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31731Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31741Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr317810x1114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31767Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31780Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr317970x1118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31796Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr318290x1120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31816Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31828Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr319320x1200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31843When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31854When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31863This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31874When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31886When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31898Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31911When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31931Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr321400x1204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31953MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31965TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31985TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr31997TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32010Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32022Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32045TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32062Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32083Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32097DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32117CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32129Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32139Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr321770x1208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32165Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32176Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr321930x120CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32192Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr322200x1210R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32209Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32219Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr322490x1214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32248When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr322630x1218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32262Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr322950x1220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32282Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32294Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr324080x1300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32309When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32322When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32335When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32348When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32361When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32373Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32387When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32407Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr327030x1304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32433MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32458BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32476Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32487TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32498TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32510ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32523TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32537Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32556Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32569PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32585Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32601Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32620Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32635CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32647Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32692Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32702Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr327400x1308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32728Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32739Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr327540x130CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32753Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr327810x1310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32770Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32780Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr328200x1314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32806Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32819Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr328360x1318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32835Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr328680x1320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32855Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32867Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr329710x1400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32882When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32893When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32902This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32913When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32925When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32937Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32950When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32970Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr331790x1404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr32992MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33004TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33024TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33036TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33049Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33061Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33084TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33101Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33122Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33136DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33156CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33168Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33178Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr332160x1408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33204Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33215Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr332320x140CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33231Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr332590x1410R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33248Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33258Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr332880x1414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33287When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr333020x1418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33301Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr333340x1420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33321Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33333Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr334470x1500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33348When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33361When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33374When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33387When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33400When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33412Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33426When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33446Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr337420x1504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33472MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33497BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33515Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33526TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33537TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33549ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33562TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33576Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33595Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33608PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33624Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33640Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33659Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33674CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33686Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33731Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33741Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr337790x1508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33767Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33778Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr337930x150CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33792Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr338200x1510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33809Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33819Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr338590x1514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33845Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33858Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr338750x1518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33874Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr339070x1520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33894Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33906Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr340100x1600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33921When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33932When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33941This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33952When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33964When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33976Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr33989When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34009Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr342180x1604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34031MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34043TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34063TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34075TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34088Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34100Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34123TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34140Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34161Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34175DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34195CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34207Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34217Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr342550x1608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34243Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34254Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr342710x160CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34270Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr342980x1610R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34287Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34297Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr343270x1614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34326When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr343410x1618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34340Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr343730x1620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34360Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34372Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr344860x1700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34387When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34400When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34413When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34426When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34439When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34451Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34465When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34485Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr347810x1704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34511MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34536BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34554Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34565TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34576TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34588ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34601TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34615Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34634Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34647PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34663Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34679Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34698Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34713CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34725Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34770Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34780Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr348180x1708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34806Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34817Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr348320x170CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34831Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr348590x1710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34848Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34858Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr348980x1714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34884Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34897Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr349140x1718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34913Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr349460x1720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34933Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34945Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr350490x1800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34960When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34971When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34980This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr34991When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35003When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35015Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35028When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35048Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr352570x1804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35070MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35082TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35102TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35114TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35127Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35139Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35162TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35179Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35200Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35214DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35234CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35246Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35256Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr352940x1808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35282Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35293Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr353100x180CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35309Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr353370x1810R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35326Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35336Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr353660x1814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35365When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr353800x1818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35379Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr354120x1820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35399Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35411Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr355250x1900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35426When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35439When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35452When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35465When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35478When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35490Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35504When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35524Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr358200x1904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35550MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35575BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35593Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35604TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35615TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35627ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35640TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35654Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35673Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35686PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35702Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35718Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35737Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35752CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35764Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35809Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35819Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr358570x1908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35845Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35856Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr358710x190CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35870Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr358980x1910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35887Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35897Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr359370x1914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35923Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35936Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr359530x1918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35952Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr359850x1920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35972Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35984Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr360880x1A00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr35999When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36010When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36019This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36030When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36042When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36054Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36067When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36087Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr362960x1A04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36109MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36121TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36141TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36153TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36166Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36178Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36201TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36218Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36239Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36253DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36273CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36285Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36295Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr363330x1A08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36321Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36332Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr363490x1A0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36348Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr363760x1A10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36365Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36375Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr364050x1A14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36404When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr364190x1A18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36418Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr364510x1A20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36438Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36450Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr365640x1B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36465When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36478When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36491When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36504When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36517When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36529Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36543When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36563Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr368590x1B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36589MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36614BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36632Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36643TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36654TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36666ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36679TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36693Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36712Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36725PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36741Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36757Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36776Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36791CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36803Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36848Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36858Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr368960x1B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36884Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36895Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr369100x1B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36909Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr369370x1B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36926Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36936Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr369760x1B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36962Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36975Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr369920x1B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr36991Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr370240x1B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37011Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37023Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr371270x1C00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37038When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37049When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37058This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37069When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37081When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37093Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37106When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37126Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr373350x1C04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37148MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37160TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37180TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37192TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37205Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37217Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37240TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37257Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37278Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37292DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37312CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37324Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37334Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr373720x1C08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37360Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37371Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr373880x1C0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37387Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr374150x1C10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37404Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37414Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr374440x1C14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37443When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr374580x1C18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37457Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr374900x1C20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37477Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37489Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr376030x1D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37504When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37517When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37530When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37543When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37556When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37568Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37582When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37602Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr378980x1D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37628MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37653BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37671Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37682TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37693TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37705ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37718TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37732Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37751Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37764PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37780Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37796Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37815Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37830CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37842Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37887Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37897Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr379350x1D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37923Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37934Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr379490x1D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37948Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr379760x1D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37965Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr37975Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr380150x1D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38001Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38014Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr380310x1D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38030Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr380630x1D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38050Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38062Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr381660x1E00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38077When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38088When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38097This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38108When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38120When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38132Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38145When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38165Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr383740x1E04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38187MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38199TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38219TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38231TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38244Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38256Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38279TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38296Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38317Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38331DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38351CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38363Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38373Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr384110x1E08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38399Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38410Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr384270x1E0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38426Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr384540x1E10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38443Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38453Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr384830x1E14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38482When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr384970x1E18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38496Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr385290x1E20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38516Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38528Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr386420x1F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38543When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38556When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38569When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38582When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38595When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38607Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38621When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38641Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr389370x1F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38667MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38692BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38710Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38721TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38732TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38744ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38757TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38771Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38790Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38803PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38819Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38835Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38854Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38869CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38881Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38926Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38936Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr389740x1F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38962Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38973Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr389880x1F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr38987Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr390150x1F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39004Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39014Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr390540x1F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39040Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39053Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr390700x1F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39069Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr391020x1F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39089Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39101Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr392150x2100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39116When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39129When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39142When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39155When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39168When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39180Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39194When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39214Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr395100x2104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39240MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39265BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39283Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39294TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39305TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39317ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39330TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39344Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39363Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39376PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39392Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39408Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39427Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39442CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39454Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39499Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39509Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr395470x2108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39535Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39546Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr395610x210CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39560Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr395880x2110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39577Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39587Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr396270x2114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39613Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39626Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr396430x2118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39642Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr396750x2120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39662Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39674Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr397880x2300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39689When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39702When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39715When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39728When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39741When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39753Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39767When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39787Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr400830x2304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39813MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39838BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39856Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39867TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39878TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39890ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39903TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39917Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39936Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39949PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39965Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr39981Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40000Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40015CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40027Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40072Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40082Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr401200x2308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40108Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40119Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr401340x230CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40133Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr401610x2310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40150Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40160Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr402000x2314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40186Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40199Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr402160x2318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40215Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr402480x2320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40235Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40247Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr403610x2500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40262When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40275When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40288When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40301When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40314When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40326Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40340When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40360Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr406560x2504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40386MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40411BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40429Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40440TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40451TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40463ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40476TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40490Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40509Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40522PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40538Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40554Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40573Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40588CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40600Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40645Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40655Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr406930x2508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40681Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40692Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr407070x250CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40706Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr407340x2510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40723Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40733Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr407730x2514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40759Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40772Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr407890x2518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40788Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr408210x2520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40808Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40820Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr409340x2700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40835When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40848When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40861When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40874When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40887When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40899Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40913When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40933Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr412290x2704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40959MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr40984BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41002Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41013TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41024TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41036ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41049TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41063Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41082Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41095PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41111Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41127Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41146Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41161CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41173Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41218Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41228Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr412660x2708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41254Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41265Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr412800x270CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41279Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr413070x2710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41296Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41306Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr413460x2714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41332Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41345Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr413620x2718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41361Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr413940x2720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41381Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41393Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr415070x2900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41408When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41421When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41434When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41447When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41460When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41472Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41486When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41506Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr418020x2904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41532MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41557BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41575Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41586TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41597TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41609ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41622TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41636Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41655Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41668PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41684Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41700Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41719Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41734CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41746Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41791Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41801Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr418390x2908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41827Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41838Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr418530x290CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41852Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr418800x2910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41869Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41879Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr419190x2914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41905Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41918Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr419350x2918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41934Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr419670x2920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41954Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41966Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr420800x2B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41981When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr41994When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42007When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42020When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42033When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42045Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42059When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42079Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr423750x2B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42105MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42130BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42148Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42159TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42170TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42182ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42195TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42209Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42228Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42241PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42257Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42273Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42292Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42307CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42319Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42364Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42374Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr424120x2B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42400Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42411Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr424260x2B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42425Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr424530x2B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42442Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42452Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr424920x2B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42478Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42491Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr425080x2B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42507Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr425400x2B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42527Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42539Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr426530x2D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42554When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42567When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42580When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42593When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42606When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42618Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42632When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42652Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr429480x2D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42678MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42703BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42721Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42732TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42743TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42755ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42768TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42782Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42801Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42814PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42830Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42846Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42865Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42880CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42892Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42937Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42947Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr429850x2D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42973Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42984Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr429990x2D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr42998Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr430260x2D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43015Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43025Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr430650x2D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43051Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43064Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr430810x2D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43080Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr431130x2D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43100Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43112Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr432260x2F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43127When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43140When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43153When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43166When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43179When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43191Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43205When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43225Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr435210x2F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43251MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43276BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43294Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43305TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43316TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43328ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43341TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43355Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43374Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43387PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43403Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43419Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43438Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43453CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43465Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43510Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43520Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr435580x2F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43546Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43557Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr435720x2F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43571Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr435990x2F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43588Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43598Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr436380x2F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43624Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43637Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr436540x2F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43653Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr436860x2F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43673Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43685Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr437990x3100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43700When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43713When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43726When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43739When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43752When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43764Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43778When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43798Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr440940x3104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43824MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43849BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43867Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43878TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43889TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43901ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43914TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43928Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43947Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43960PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43976Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr43992Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44011Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44026CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44038Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44083Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44093Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr441310x3108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44119Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44130Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr441450x310CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44144Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr441720x3110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44161Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44171Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr442110x3114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44197Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44210Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr442270x3118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44226Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr442590x3120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44246Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44258Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr443720x3300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44273When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44286When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44299When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44312When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44325When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44337Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44351When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44371Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr446670x3304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44397MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44422BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44440Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44451TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44462TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44474ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44487TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44501Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44520Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44533PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44549Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44565Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44584Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44599CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44611Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44656Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44666Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr447040x3308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44692Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44703Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr447180x330CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44717Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr447450x3310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44734Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44744Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr447840x3314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44770Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44783Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr448000x3318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44799Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr448320x3320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44819Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44831Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr449450x3500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44846When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44859When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44872When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44885When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44898When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44910Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44924When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44944Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr452400x3504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44970MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr44995BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45013Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45024TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45035TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45047ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45060TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45074Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45093Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45106PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45122Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45138Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45157Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45172CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45184Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45229Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45239Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr452770x3508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45265Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45276Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr452910x350CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45290Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr453180x3510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45307Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45317Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr453570x3514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45343Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45356Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr453730x3518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45372Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr454050x3520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45392Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45404Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr455180x3700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45419When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45432When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45445When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45458When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45471When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45483Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45497When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45517Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr458130x3704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45543MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45568BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45586Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45597TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45608TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45620ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45633TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45647Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45666Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45679PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45695Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45711Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45730Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45745CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45757Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45802Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45812Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr458500x3708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45838Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45849Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr458640x370CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45863Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr458910x3710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45880Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45890Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr459300x3714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45916Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45929Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr459460x3718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45945Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr459780x3720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45965Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45977Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr460910x3900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr45992When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46005When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46018When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46031When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46044When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46056Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46070When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46090Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr463860x3904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46116MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46141BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46159Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46170TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46181TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46193ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46206TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46220Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46239Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46252PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46268Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46284Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46303Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46318CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46330Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46375Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46385Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr464230x3908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46411Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46422Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr464370x390CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46436Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr464640x3910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46453Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46463Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr465030x3914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46489Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46502Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr465190x3918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46518Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr465510x3920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46538Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46550Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr466640x3B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46565When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46578When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46591When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46604When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46617When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46629Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46643When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46663Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr469590x3B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46689MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46714BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46732Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46743TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46754TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46766ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46779TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46793Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46812Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46825PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46841Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46857Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46876Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46891CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46903Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46948Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46958Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr469960x3B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46984Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr46995Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr470100x3B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47009Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr470370x3B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47026Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47036Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr470760x3B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47062Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47075Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr470920x3B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47091Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr471240x3B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47111Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47123Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr472370x3D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47138When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47151When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47164When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47177When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47190When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47202Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47216When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47236Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr475320x3D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47262MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47287BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47305Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47316TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47327TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47339ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47352TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47366Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47385Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47398PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47414Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47430Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47449Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47464CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47476Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47521Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47531Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr475690x3D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47557Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47568Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr475830x3D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47582Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr476100x3D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47599Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47609Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr476490x3D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47635Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47648Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr476650x3D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47664Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr476970x3D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47684Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47696Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr478100x3F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47711When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47724When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47737When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47750When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47763When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47775Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47789When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47809Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr481050x3F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47835MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47860BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47878Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47889TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47900TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47912ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47925TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47939Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47958Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47971PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr47987Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48003Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48022Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48037CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48049Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48094Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48104Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr481420x3F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48130Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48141Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr481560x3F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48155Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr481830x3F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48172Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48182Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr482220x3F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48208Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48221Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr482380x3F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48237Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr482700x3F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48257Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48269Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAPPF0_DMA_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr546190x380000R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAPDMA Port Logic StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFDMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr483490x0R/W0x00000688PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFFDMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx Requests - DMA Write Channel MRd Requests (DMA data requests and LL element/descriptor access) - DMA Read Channel MRd Requests (LL element/descriptor access) - DMA Read Channel MWr RequestsConcurrent traffic from channels with same priority are sorted according to Round-Robin arbitration rules.The arbitration priority defaults to Non-DMA requests (highest), Write Channel MRd, Read Channel MRd, Read Channel MWr.For more details, see the For more details, see the Internal Architecture section in the DMA chapter of the Databook.falsefalsefalsefalseRTRGT1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48305Non-DMA Rx Requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0R/WWR_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48317DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 530x1R/WRD_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48329DMA Read Channel MRd Requests. For LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 860x2R/WRDBUFF_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48340DMA Read Channel MWr Requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1190x3R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48348Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFDMA_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr484250x8R/W0x00040004PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CTRL_OFFDMA Number of Channels Register.falsefalsefalsefalseNUM_DMA_WR_CHANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48362Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support.300x4RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48370Reserved for future use.1540x000RNUM_DMA_RD_CHANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48380Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support.19160x4RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48388Reserved for future use.23200x0RDIS_C2W_CACHE_WRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48402Disable DMA Write Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDIS_C2W_CACHE_RDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48416Disable DMA Read Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48424Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFDMA_WRITE_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr485840xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFFDMA Write Engine Enable Register.falsefalsefalsefalseDMA_WRITE_ENGINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48479DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this bit to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the DMA controller write logic re-initializes the control logic, ensuring that the next DMA write transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" , after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped." Resetting the DMA controller write logic re-initializes the control logic ensuring that the next DMA write transfer is executed successfully. - During software development, when you incorrectly program the DMA write engine.To "Soft Reset" the DMA controller write logic, you must: - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert the DMA write engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48487Reserved for future use.1510x0000RDMA_WRITE_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48498Enable Handshake for DMA Write Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16160x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48509Enable Handshake for DMA Write Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 17170x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48520Enable Handshake for DMA Write Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 18180x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48531Enable Handshake for DMA Write Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19190x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48542Enable Handshake for DMA Write Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 20200x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48553Enable Handshake for DMA Write Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21210x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48564Enable Handshake for DMA Write Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48575Enable Handshake for DMA Write Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48583Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFDMA_WRITE_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr486370x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFFDMA Write Doorbell Register.falsefalsefalsefalseWR_DOORBELL_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48607Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to toggle or write any other value to this register to start a new transfer.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48615Reserved for future use.3030x0000000RWR_STOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48636Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)."Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr487190x18R/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48665Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WWRITE_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48680Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WWRITE_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48695Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WWRITE_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48710Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48718Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr488010x1CR/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48747Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WWRITE_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48762Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WWRITE_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48777Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WWRITE_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48792Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48800Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFDMA_READ_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr489590x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFFDMA Read Engine Enable Register.falsefalsefalsefalseDMA_READ_ENGINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48854DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this field to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the DMA controller read logic re-initializes the control logic, ensuring that the next DMA read transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit", after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped". Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA read transfer is executed successfully. - During software development, when you incorrectly program the DMA read engine.To "Soft Reset" the DMA controller read logic, you must: - De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA read engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA read transfer does not start until you write to the "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48862Reserved for future use.1510x0000RDMA_READ_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48873Enable Handshake for DMA Read Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16160x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48884Enable Handshake for DMA Read Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 17170x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48895Enable Handshake for DMA Read Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 18180x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48906Enable Handshake for DMA Read Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19190x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48917Enable Handshake for DMA Read Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 20200x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48928Enable Handshake for DMA Read Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21210x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48939Enable Handshake for DMA Read Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48950Enable Handshake for DMA Read Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48958Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFDMA_READ_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr490100x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DOORBELL_OFFDMA Read Doorbell Register.falsefalsefalsefalseRD_DOORBELL_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48980Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr48988Reserved for future use.3030x0000000RRD_STOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49009Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr490870x38R/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49036Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WREAD_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49050Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WREAD_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49064Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WREAD_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49078Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49086Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr491640x3CR/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49113Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WREAD_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49127Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WREAD_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49141Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WREAD_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49155Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49163Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFDMA_WRITE_INT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr492380x4CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFFDMA Write Interrupt Status Register.falsefalsefalsefalseWR_DONE_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49194Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49202Reserved for future use.1580x00RWR_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49229Abort Interrupt Status. The DMA write channel has detected an error, or you manually stopped the transfer as described in "Error Handling Assistance by Remote Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49237Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFDMA_WRITE_INT_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr492860x54R/W0x000f000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFFDMA Write Interrupt Mask Register.falsefalsefalsefalseWR_DONE_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49255Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49263Reserved for future use.1580x00RWR_ABORT_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49277Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49285Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFDMA_WRITE_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr493380x58R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFFDMA Write Interrupt Clear Register.falsefalsefalsefalseWR_DONE_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49305Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".300x0W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49313Reserved for future use.1580x00RWR_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49329Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".19160x0W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49337Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFDMA_WRITE_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr494000x5CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFFDMA Write Error Status RegisterfalsefalsefalsefalseAPP_READ_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49363Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49370Reserved for future use.1580x00RLINKLIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49392Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49399Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFDMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr494170x60R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFFDMA Write Done IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_DONE_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49416The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFDMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr494330x64R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFFDMA Write Done IMWr Interrupt Address High Register.falsefalsefalsefalseDMA_WRITE_DONE_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49432The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFDMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr494510x68R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFFDMA Write Abort IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_ABORT_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49450The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr494670x6CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA Write Abort IMWr Address High Register.falsefalsefalsefalseDMA_WRITE_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49466The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFDMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr494950x70R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFFDMA Write Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49482The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49494The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFDMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr495230x74R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFFDMA Write Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49510The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49522The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFDMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr495510x78R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFFDMA Write Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49538The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49550The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFDMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr495790x7CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFFDMA Write Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49566The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49578The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr496370x90R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseWR_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49603Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49611Reserved for future use.1580x00RWR_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49628Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49636Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFDMA_READ_INT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr497140xA0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFFDMA Read Interrupt Status Register.falsefalsefalsefalseRD_DONE_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49666Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49674Reserved for future use.1580x00RRD_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49705Abort Interrupt Status. The DMA read channel has detected an error, or you manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.You can read the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49713Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFDMA_READ_INT_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr497620xA8R/W0x000f000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_MASK_OFFDMA Read Interrupt Mask Register.falsefalsefalsefalseRD_DONE_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49731Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49739Reserved for future use.1580x00RRD_ABORT_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49753Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49761Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFDMA_READ_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr498140xACR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFFDMA Read Interrupt Clear Register.falsefalsefalsefalseRD_DONE_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49781Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".700x00WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49789Reserved for future use.1580x00RRD_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49805Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".23160x00WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49813Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFDMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr498820xB4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFFDMA Read Error Status Low Register.falsefalsefalsefalseAPP_WR_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49844Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer from the beginning, as the channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49851Reserved for future use.1580x00RLINK_LIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49874Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49881Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFDMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr499830xB8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFFDMA Read Error Status High Register.falsefalsefalsefalseUNSUPPORTED_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49909Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.700x00RCPL_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49933Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode".Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.1580x00RCPL_TIMEOUTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49956Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request, or a malformed CplD has been received. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.23160x00RDATA_POISIONINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr49982Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request).The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFDMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr500400xC4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFFDMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseRD_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50006Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50014Reserved for future use.1580x00RRD_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50031Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50039Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFDMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr500570xCCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFFDMA Read Done IMWr Address Low Register.falsefalsefalsefalseDMA_READ_DONE_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50056The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFDMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr500730xD0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFFDMA Read Done IMWr Address High Register.falsefalsefalsefalseDMA_READ_DONE_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50072The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFDMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr500900xD4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFFDMA Read Abort IMWr Address Low Register.falsefalsefalsefalseDMA_READ_ABORT_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50089The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFDMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr501060xD8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFFDMA Read Abort IMWr Address High Register.falsefalsefalsefalseDMA_READ_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50105The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFDMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr501340xDCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFFDMA Read Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50121The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50133The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFDMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr501620xE0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFFDMA Read Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50149The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50161The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFDMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr501900xE4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFFDMA Read Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50177The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50189The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFDMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr502180xE8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFFDMA Read Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50205The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50217The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr502910x108R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA Write Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50232DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50239Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50249DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50256Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50266DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50273Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50283DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50290Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr503640x10CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Write Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50305DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50312Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50322DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50329Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50339DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50346Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50356DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50363Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr504370x118R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA Read Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50378DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50385Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50395DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50402Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50412DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50419Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50429DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50436Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr505100x11CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Read Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50451DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50458Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50468DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50475Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50485DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50492Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50502DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50509Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr508170x200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50530Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50549Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50566Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50587Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50608Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50629Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50641Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50659Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50672Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50684Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50700Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50712Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50734Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50748Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50762Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50776Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50788Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50802Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50816Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr508730x204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50833Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50845Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50858Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50872TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr509040x208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50903DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr509250x20CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50924Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr509430x210R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50942Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr509640x214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50963Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr509830x218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr50982Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr510050x21CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51004Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr510240x220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51023Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr513310x300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51044Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51063Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51080Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51101Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51122Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51143Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51155Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51173Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51186Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51198Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51214Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51226Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51248Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51262Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51276Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51290Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51302Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51316Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51330Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr513870x304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51347Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51359Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51372Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51386TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr514180x308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51417DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr514390x30CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51438Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr514570x310R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51456Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr514780x314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51477Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr514960x318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51495Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr515180x31CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51517Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr515370x320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51536Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr518440x400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51557Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51576Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51593Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51614Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51635Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51656Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51668Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51686Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51699Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51711Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51727Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51739Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51761Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51775Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51789Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51803Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51815Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51829Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51843Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr519000x404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51860Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51872Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51885Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51899TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr519310x408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51930DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr519520x40CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51951Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr519700x410R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51969Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr519910x414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr51990Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr520100x418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52009Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr520320x41CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52031Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr520510x420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52050Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr523580x500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52071Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52090Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52107Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52128Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52149Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52170Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52182Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52200Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52213Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52225Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52241Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52253Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52275Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52289Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52303Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52317Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52329Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52343Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52357Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr524140x504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52374Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52386Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52399Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52413TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr524450x508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52444DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr524660x50CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52465Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr524840x510R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52483Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr525050x514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52504Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr525230x518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52522Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr525450x51CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52544Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr525640x520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52563Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr528710x600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52584Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52603Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52620Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52641Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52662Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52683Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52695Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52713Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52726Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52738Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52754Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52766Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52788Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52802Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52816Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52830Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52842Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52856Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52870Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr529270x604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52887Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52899Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52912Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52926TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr529580x608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52957DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr529790x60CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52978Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr529970x610R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr52996Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr530180x614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53017Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr530370x618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53036Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr530590x61CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53058Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr530780x620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53077Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr533850x700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53098Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53117Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53134Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53155Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53176Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53197Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53209Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53227Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53240Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53252Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53268Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53280Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53302Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53316Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53330Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53344Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53356Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53370Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53384Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr534410x704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53401Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53413Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53426Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53440TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr534720x708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53471DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr534930x70CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53492Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr535110x710R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53510Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr535320x714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53531Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr535500x718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53549Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr535720x71CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53571Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr535910x720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53590Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr538980x800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53611Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53630Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53647Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53668Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53689Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53710Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53722Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53740Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53753Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53765Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53781Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53793Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53815Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53829Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53843Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53857Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53869Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53883Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53897Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr539540x804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53914Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53926Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53939Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53953TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr539850x808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr53984DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr540060x80CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54005Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr540240x810R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54023Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr540450x814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54044Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr540640x818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54063Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr540860x81CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54085Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr541050x820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54104Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr544120x900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54125Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54144Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54161Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54182Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54203Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54224Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54236Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54254Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54267Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54279Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54295Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54307Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54329Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54343Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54357Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54371Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54383Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54397Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54411Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr544680x904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54428Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54440Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54453Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54467TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr544990x908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54498DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr545200x90CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54519Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr545380x910R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54537Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr545590x914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54558Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr545770x918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54576Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr545990x91CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54598Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr546180x920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54617Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WaddressmapPE0_DWC_pcie_ctl.DBI_SlaveDBI_SlaveDWC_pcie_dbi_cpcie_dsp_4x8.csr109230R/WPE0_DWC_pcie_ctl_DBI_SlaveDWC PCIE-RC Memory MapgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDRgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGICmemoryPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP_DBI2groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP0x00x381123DBI_SlavePE0_DWC_pcie_ctl.DBI_Slave0x00x3FDBI_Slave.PF0_TYPE1_HDRPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR0x00x0DBI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REG0x40x4DBI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REG0x80x8DBI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REG0xC0xCDBI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG0x100x10DBI_Slave.PF0_TYPE1_HDR.BAR0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BAR0_REG0x140x14DBI_Slave.PF0_TYPE1_HDR.BAR1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BAR1_REG0x180x18DBI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG0x1C0x1CDBI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REG0x200x20DBI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REG0x240x24DBI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REG0x280x28DBI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REG0x2C0x2CDBI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REG0x300x30DBI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REG0x340x34DBI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REG0x380x38DBI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REG0x3C0x3CDBI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REG0x400x47DBI_Slave.PF0_PM_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP0x400x40DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REG0x440x44DBI_Slave.PF0_PM_CAP.CON_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CON_STATUS_REG0x480x4F0x500x67DBI_Slave.PF0_MSI_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP0x500x50DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REG0x540x54DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REG0x580x58DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REG0x5C0x5CDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REG0x600x60DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REG0x640x64DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REG0x680x6F0x700xABDBI_Slave.PF0_PCIE_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP0x700x70DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG0x740x74DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REG0x780x78DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUS0x7C0x7CDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REG0x800x80DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REG0x840x84DBI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REG0x880x88DBI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUSPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUS0x8C0x8CDBI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REG0x900x90DBI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REG0x940x94DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REG0x980x98DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REG0x9C0x9CDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REG0xA00xA0DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REG0xA40xAB0xAC0xAF0xB00xBCDBI_Slave.PF0_MSIX_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP0xB00xB0DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REG0xB40xB4DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REG0xB80xB8DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REG0xBC0xBC0xBD0xFF0x1000x147DBI_Slave.PF0_AER_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP0x1000x100DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFF0x1040x104DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFF0x1080x108DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFF0x10C0x10CDBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFF0x1100x110DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFF0x1140x114DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFF0x1180x118DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFF0x11C0x11CDBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFF0x1200x120DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFF0x1240x124DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFF0x1280x128DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFF0x12C0x12CDBI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFF0x1300x130DBI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFF0x1340x134DBI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFF0x1380x138DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFF0x13C0x13CDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFF0x1400x140DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFF0x1440x144DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFF0x1480x197DBI_Slave.PF0_VC_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP0x1480x148DBI_Slave.PF0_VC_CAP.VC_BASEPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_BASE0x14C0x14CDBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_10x1500x150DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_20x1540x154DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REG0x1580x158DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC00x15C0x15CDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC00x1600x160DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC00x1640x164DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC10x1680x168DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC10x16C0x16CDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC10x1700x170DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC20x1740x174DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC20x1780x178DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC20x17C0x17CDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC30x1800x180DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC30x1840x184DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3PE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC30x1880x1970x1980x1B7DBI_Slave.PF0_SPCIE_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP0x1980x198DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REG0x19C0x19CDBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REG0x1A00x1A0DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REG0x1A40x1A4DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REG0x1A80x1A8DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REG0x1AC0x1ACDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REG0x1B00x1B0DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REG0x1B40x1B70x1B80x1DFDBI_Slave.PF0_PL16G_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP0x1B80x1B8DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REG0x1BC0x1BCDBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REG0x1C00x1C0DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REG0x1C40x1C4DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REG0x1C80x1C8DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REG0x1CC0x1CCDBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REG0x1D00x1D0DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REG0x1D40x1D70x1D80x1D8DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REG0x1DC0x1DCDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REG0x1E00x207DBI_Slave.PF0_MARGIN_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP0x1E00x1E0DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REG0x1E40x1E4DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REG0x1E80x1E8DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REG0x1EC0x1ECDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REG0x1F00x1F0DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REG0x1F40x1F4DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REG0x1F80x1F8DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REG0x1FC0x1FCDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REG0x2000x200DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REG0x2040x204DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REG0x2080x293DBI_Slave.PF0_TPH_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP0x2080x208DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REG0x20C0x20CDBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REG0x2100x210DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REG0x2140x214DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_00x2180x2930x2940x29B0x29C0x2ABDBI_Slave.PF0_L1SUB_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP0x29C0x29CDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REG0x2A00x2A0DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REG0x2A40x2A4DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REG0x2A80x2A8DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REG0x2AC0x2BBDBI_Slave.PF0_FRSQ_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP0x2AC0x2ACDBI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFF0x2B00x2B0DBI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFF0x2B40x2B4DBI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFF0x2B80x2B8DBI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFF0x2BC0x2C30x2C40x3C3DBI_Slave.PF0_RAS_DES_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP0x2C40x2C4DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REG0x2C80x2C8DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REG0x2CC0x2CCDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REG0x2D00x2D0DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REG0x2D40x2D4DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REG0x2D80x2D8DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REG0x2DC0x2DCDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REG0x2E00x2F30x2F40x2F4DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REG0x2F80x2F8DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REG0x2FC0x2FCDBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REG0x3000x300DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REG0x3040x304DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REG0x3080x308DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REG0x30C0x30CDBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REG0x3100x310DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REG0x3140x314DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REG0x3180x318DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REG0x31C0x31CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REG0x3200x320DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REG0x3240x324DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REG0x3280x328DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REG0x32C0x32CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REG0x3300x330DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REG0x3340x334DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REG0x3380x338DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REG0x33C0x33CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REG0x3400x340DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REG0x3440x344DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REG0x3480x348DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REG0x34C0x34CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REG0x3500x350DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REG0x3540x3630x3640x364DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REG0x3680x368DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REG0x36C0x3730x3740x374DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REG0x3780x378DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REG0x37C0x37CDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REG0x3800x380DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REG0x3840x384DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REG0x3880x388DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REG0x38C0x3930x3940x394DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REG0x3980x398DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REG0x39C0x39CDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REG0x3A00x3A30x3A40x3A4DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REG0x3A80x3A8DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REG0x3AC0x3ACDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REG0x3B00x3C30x3C40x3FBDBI_Slave.PF0_VSECRAS_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP0x3C40x3C4DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFF0x3C80x3C8DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFF0x3CC0x3CCDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFF0x3D00x3D0DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFF0x3D40x3D4DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFF0x3D80x3D8DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFF0x3DC0x3DCDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFF0x3E00x3E0DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFF0x3E40x3E4DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFF0x3E80x3E8DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFF0x3EC0x3ECDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFF0x3F00x3F0DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFF0x3F40x3F4DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFF0x3F80x3F8DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFF0x3FC0x407DBI_Slave.PF0_DLINK_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP0x3FC0x3FCDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFF0x4000x400DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFF0x4040x404DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFF0x4080x6FF0x7000xCFFDBI_Slave.PF0_PORT_LOGICPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC0x7000x700DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFF0x7040x704DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFF0x7080x708DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFF0x70C0x70CDBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFF0x7100x710DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFF0x7140x714DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFF0x7180x718DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFF0x71C0x71CDBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFF0x7200x720DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFF0x7240x724DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF0x7280x728DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFF0x72C0x72CDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFF0x7300x730DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFF0x7340x734DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFF0x7380x738DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFF0x73C0x73CDBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFF0x7400x740DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFF0x7440x744DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFF0x7480x748DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFF0x74C0x74CDBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFF0x7500x750DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFF0x7540x754DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFF0x7580x758DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFF0x75C0x75CDBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFF0x7600x760DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFF0x7640x764DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFF0x7680x768DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFF0x76C0x76CDBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFF0x7700x770DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFF0x7740x774DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFF0x7780x80B0x80C0x80CDBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFF0x8100x810DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFF0x8140x814DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFF0x8180x81B0x81C0x81CDBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFF0x8200x820DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFF0x8240x824DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFF0x8280x828DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFF0x82C0x82CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFF0x8300x830DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFF0x8340x834DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFF0x8380x838DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFF0x83C0x83CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFF0x8400x840DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFF0x8440x844DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFF0x8480x848DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFF0x84C0x84CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFF0x8500x850DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFF0x8540x854DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFF0x8580x858DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFF0x85C0x85CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFF0x8600x860DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFF0x8640x864DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFF0x8680x868DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFF0x86C0x86CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFF0x8700x870DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFF0x8740x874DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFF0x8780x878DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFF0x87C0x87CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFF0x8800x880DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFF0x8840x884DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFF0x8880x888DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFF0x88C0x88CDBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFF0x8900x890DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFF0x8940x8A70x8A80x8A8DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFF0x8AC0x8ACDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFF0x8B00x8B30x8B40x8B4DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFF0x8B80x8B8DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFF0x8BC0x8BCDBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFF0x8C00x8C0DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFF0x8C40x8C4DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFF0x8C80x8C8DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFF0x8CC0x8CCDBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFF0x8D00x8D0DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFF0x8D40x8D4DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFF0x8D80x8D8DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFF0x8DC0x8DF0x8E00x8E0DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFF0x8E40x8E4DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFF0x8E80x8E8DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFF0x8EC0x8EF0x8F00x8F0DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFF0x8F40x8F4DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFF0x8F80x8F8DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFF0x8FC0x8FCDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFF0x9000x93F0x9400x940DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFF0x9440x944DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFF0x9480x948DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFF0x94C0x94CDBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFF0x9500xB2F0xB300xB30DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFF0xB340xB3F0xB400xB40DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFF0xB440xB44DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFF0xB480xB48DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFF0xB4C0xB7F0xB800xB80DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFF0xB840xB84DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFF0xB880xB8F0xB900xB90DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFF0xB940xCFF0xD000x10006F0x1000700x1000ABDBI_Slave.PF0_PCIE_CAP_DBI2PE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP_DBI20x1000AC0x1000AF0x1000B00x1000BCDBI_Slave.PF0_MSIX_CAP_DBI2PE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI20x1000B00x1000B0DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG0x1000B40x1000B4DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REG0x1000B80x1000B8DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REG0x1000BC0x1000BC0x1000BD0x1002070x1002080x100293DBI_Slave.PF0_TPH_CAP_DBI2PE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI20x1002080x10020B0x10020C0x10020CDBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REG0x1002100x1002930x1002940x2FFFFF0x3000000x31FF23DBI_Slave.PF0_ATU_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP0x3000000x300000DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_00x3000040x300004DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_00x3000080x300008DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_00x30000C0x30000CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_00x3000100x300010DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_00x3000140x300014DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_00x3000180x300018DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_00x30001C0x30001F0x3000200x300020DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_00x3000240x3000FF0x3001000x300100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_00x3001040x300104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_00x3001080x300108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_00x30010C0x30010CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_00x3001100x300110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_00x3001140x300114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_00x3001180x300118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_00x30011C0x30011F0x3001200x300120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_00x3001240x3001FF0x3002000x300200DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10x3002040x300204DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10x3002080x300208DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10x30020C0x30020CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10x3002100x300210DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10x3002140x300214DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10x3002180x300218DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10x30021C0x30021F0x3002200x300220DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10x3002240x3002FF0x3003000x300300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10x3003040x300304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10x3003080x300308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10x30030C0x30030CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10x3003100x300310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10x3003140x300314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10x3003180x300318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10x30031C0x30031F0x3003200x300320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10x3003240x3003FF0x3004000x300400DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_20x3004040x300404DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_20x3004080x300408DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_20x30040C0x30040CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_20x3004100x300410DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_20x3004140x300414DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_20x3004180x300418DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_20x30041C0x30041F0x3004200x300420DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_20x3004240x3004FF0x3005000x300500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20x3005040x300504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20x3005080x300508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20x30050C0x30050CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20x3005100x300510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20x3005140x300514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20x3005180x300518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20x30051C0x30051F0x3005200x300520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20x3005240x3005FF0x3006000x300600DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_30x3006040x300604DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_30x3006080x300608DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_30x30060C0x30060CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_30x3006100x300610DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_30x3006140x300614DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_30x3006180x300618DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_30x30061C0x30061F0x3006200x300620DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_30x3006240x3006FF0x3007000x300700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30x3007040x300704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30x3007080x300708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30x30070C0x30070CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30x3007100x300710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30x3007140x300714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30x3007180x300718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30x30071C0x30071F0x3007200x300720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30x3007240x3007FF0x3008000x300800DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_40x3008040x300804DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_40x3008080x300808DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_40x30080C0x30080CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_40x3008100x300810DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_40x3008140x300814DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_40x3008180x300818DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_40x30081C0x30081F0x3008200x300820DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_40x3008240x3008FF0x3009000x300900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_40x3009040x300904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_40x3009080x300908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_40x30090C0x30090CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_40x3009100x300910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_40x3009140x300914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_40x3009180x300918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_40x30091C0x30091F0x3009200x300920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_40x3009240x3009FF0x300A000x300A00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_50x300A040x300A04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_50x300A080x300A08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_50x300A0C0x300A0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_50x300A100x300A10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_50x300A140x300A14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_50x300A180x300A18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_50x300A1C0x300A1F0x300A200x300A20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_50x300A240x300AFF0x300B000x300B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_50x300B040x300B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_50x300B080x300B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_50x300B0C0x300B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_50x300B100x300B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_50x300B140x300B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_50x300B180x300B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_50x300B1C0x300B1F0x300B200x300B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_50x300B240x300BFF0x300C000x300C00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_60x300C040x300C04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_60x300C080x300C08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_60x300C0C0x300C0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_60x300C100x300C10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_60x300C140x300C14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_60x300C180x300C18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_60x300C1C0x300C1F0x300C200x300C20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_60x300C240x300CFF0x300D000x300D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_60x300D040x300D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_60x300D080x300D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_60x300D0C0x300D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_60x300D100x300D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_60x300D140x300D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_60x300D180x300D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_60x300D1C0x300D1F0x300D200x300D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_60x300D240x300DFF0x300E000x300E00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_70x300E040x300E04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_70x300E080x300E08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_70x300E0C0x300E0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_70x300E100x300E10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_70x300E140x300E14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_70x300E180x300E18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_70x300E1C0x300E1F0x300E200x300E20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_70x300E240x300EFF0x300F000x300F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_70x300F040x300F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_70x300F080x300F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_70x300F0C0x300F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_70x300F100x300F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_70x300F140x300F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_70x300F180x300F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_70x300F1C0x300F1F0x300F200x300F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_70x300F240x300FFF0x3010000x301000DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_80x3010040x301004DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_80x3010080x301008DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_80x30100C0x30100CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_80x3010100x301010DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_80x3010140x301014DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_80x3010180x301018DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_80x30101C0x30101F0x3010200x301020DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_80x3010240x3010FF0x3011000x301100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_80x3011040x301104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_80x3011080x301108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_80x30110C0x30110CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_80x3011100x301110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_80x3011140x301114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_80x3011180x301118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_80x30111C0x30111F0x3011200x301120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_80x3011240x3011FF0x3012000x301200DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_90x3012040x301204DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_90x3012080x301208DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_90x30120C0x30120CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_90x3012100x301210DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_90x3012140x301214DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_90x3012180x301218DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_90x30121C0x30121F0x3012200x301220DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_90x3012240x3012FF0x3013000x301300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_90x3013040x301304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_90x3013080x301308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_90x30130C0x30130CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_90x3013100x301310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_90x3013140x301314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_90x3013180x301318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_90x30131C0x30131F0x3013200x301320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_90x3013240x3013FF0x3014000x301400DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_100x3014040x301404DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_100x3014080x301408DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_100x30140C0x30140CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_100x3014100x301410DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_100x3014140x301414DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_100x3014180x301418DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_100x30141C0x30141F0x3014200x301420DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_100x3014240x3014FF0x3015000x301500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_100x3015040x301504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_100x3015080x301508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_100x30150C0x30150CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_100x3015100x301510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_100x3015140x301514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_100x3015180x301518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_100x30151C0x30151F0x3015200x301520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_100x3015240x3015FF0x3016000x301600DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_110x3016040x301604DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_110x3016080x301608DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_110x30160C0x30160CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_110x3016100x301610DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_110x3016140x301614DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_110x3016180x301618DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_110x30161C0x30161F0x3016200x301620DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_110x3016240x3016FF0x3017000x301700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_110x3017040x301704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_110x3017080x301708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_110x30170C0x30170CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_110x3017100x301710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_110x3017140x301714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_110x3017180x301718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_110x30171C0x30171F0x3017200x301720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_110x3017240x3017FF0x3018000x301800DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_120x3018040x301804DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_120x3018080x301808DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_120x30180C0x30180CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_120x3018100x301810DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_120x3018140x301814DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_120x3018180x301818DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_120x30181C0x30181F0x3018200x301820DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_120x3018240x3018FF0x3019000x301900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_120x3019040x301904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_120x3019080x301908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_120x30190C0x30190CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_120x3019100x301910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_120x3019140x301914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_120x3019180x301918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_120x30191C0x30191F0x3019200x301920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_120x3019240x3019FF0x301A000x301A00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_130x301A040x301A04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_130x301A080x301A08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_130x301A0C0x301A0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_130x301A100x301A10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_130x301A140x301A14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_130x301A180x301A18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_130x301A1C0x301A1F0x301A200x301A20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_130x301A240x301AFF0x301B000x301B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_130x301B040x301B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_130x301B080x301B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_130x301B0C0x301B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_130x301B100x301B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_130x301B140x301B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_130x301B180x301B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_130x301B1C0x301B1F0x301B200x301B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_130x301B240x301BFF0x301C000x301C00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_140x301C040x301C04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_140x301C080x301C08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_140x301C0C0x301C0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_140x301C100x301C10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_140x301C140x301C14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_140x301C180x301C18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_140x301C1C0x301C1F0x301C200x301C20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_140x301C240x301CFF0x301D000x301D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_140x301D040x301D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_140x301D080x301D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_140x301D0C0x301D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_140x301D100x301D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_140x301D140x301D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_140x301D180x301D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_140x301D1C0x301D1F0x301D200x301D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_140x301D240x301DFF0x301E000x301E00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_150x301E040x301E04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_150x301E080x301E08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_150x301E0C0x301E0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_150x301E100x301E10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_150x301E140x301E14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_150x301E180x301E18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_150x301E1C0x301E1F0x301E200x301E20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_150x301E240x301EFF0x301F000x301F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_150x301F040x301F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_150x301F080x301F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_150x301F0C0x301F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_150x301F100x301F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_150x301F140x301F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_150x301F180x301F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_150x301F1C0x301F1F0x301F200x301F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_150x301F240x3020FF0x3021000x302100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_160x3021040x302104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_160x3021080x302108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_160x30210C0x30210CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_160x3021100x302110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_160x3021140x302114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_160x3021180x302118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_160x30211C0x30211F0x3021200x302120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_160x3021240x3022FF0x3023000x302300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_170x3023040x302304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_170x3023080x302308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_170x30230C0x30230CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_170x3023100x302310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_170x3023140x302314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_170x3023180x302318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_170x30231C0x30231F0x3023200x302320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_170x3023240x3024FF0x3025000x302500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_180x3025040x302504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_180x3025080x302508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_180x30250C0x30250CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_180x3025100x302510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_180x3025140x302514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_180x3025180x302518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_180x30251C0x30251F0x3025200x302520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_180x3025240x3026FF0x3027000x302700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_190x3027040x302704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_190x3027080x302708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_190x30270C0x30270CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_190x3027100x302710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_190x3027140x302714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_190x3027180x302718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_190x30271C0x30271F0x3027200x302720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_190x3027240x3028FF0x3029000x302900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_200x3029040x302904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_200x3029080x302908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_200x30290C0x30290CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_200x3029100x302910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_200x3029140x302914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_200x3029180x302918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_200x30291C0x30291F0x3029200x302920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_200x3029240x302AFF0x302B000x302B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_210x302B040x302B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_210x302B080x302B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_210x302B0C0x302B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_210x302B100x302B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_210x302B140x302B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_210x302B180x302B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_210x302B1C0x302B1F0x302B200x302B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_210x302B240x302CFF0x302D000x302D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_220x302D040x302D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_220x302D080x302D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_220x302D0C0x302D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_220x302D100x302D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_220x302D140x302D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_220x302D180x302D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_220x302D1C0x302D1F0x302D200x302D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_220x302D240x302EFF0x302F000x302F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_230x302F040x302F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_230x302F080x302F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_230x302F0C0x302F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_230x302F100x302F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_230x302F140x302F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_230x302F180x302F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_230x302F1C0x302F1F0x302F200x302F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_230x302F240x3030FF0x3031000x303100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_240x3031040x303104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_240x3031080x303108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_240x30310C0x30310CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_240x3031100x303110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_240x3031140x303114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_240x3031180x303118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_240x30311C0x30311F0x3031200x303120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_240x3031240x3032FF0x3033000x303300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_250x3033040x303304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_250x3033080x303308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_250x30330C0x30330CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_250x3033100x303310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_250x3033140x303314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_250x3033180x303318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_250x30331C0x30331F0x3033200x303320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_250x3033240x3034FF0x3035000x303500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_260x3035040x303504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_260x3035080x303508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_260x30350C0x30350CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_260x3035100x303510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_260x3035140x303514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_260x3035180x303518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_260x30351C0x30351F0x3035200x303520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_260x3035240x3036FF0x3037000x303700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_270x3037040x303704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_270x3037080x303708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_270x30370C0x30370CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_270x3037100x303710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_270x3037140x303714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_270x3037180x303718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_270x30371C0x30371F0x3037200x303720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_270x3037240x3038FF0x3039000x303900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_280x3039040x303904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_280x3039080x303908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_280x30390C0x30390CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_280x3039100x303910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_280x3039140x303914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_280x3039180x303918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_280x30391C0x30391F0x3039200x303920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_280x3039240x303AFF0x303B000x303B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_290x303B040x303B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_290x303B080x303B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_290x303B0C0x303B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_290x303B100x303B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_290x303B140x303B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_290x303B180x303B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_290x303B1C0x303B1F0x303B200x303B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_290x303B240x303CFF0x303D000x303D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_300x303D040x303D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_300x303D080x303D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_300x303D0C0x303D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_300x303D100x303D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_300x303D140x303D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_300x303D180x303D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_300x303D1C0x303D1F0x303D200x303D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_300x303D240x303EFF0x303F000x303F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_310x303F040x303F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_310x303F080x303F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_310x303F0C0x303F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_310x303F100x303F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_310x303F140x303F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_310x303F180x303F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_310x303F1C0x303F1F0x303F200x303F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_310x303F240x31FF230x31FF240x37FFFF0x3800000x381123DBI_Slave.PF0_DMA_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP0x3800000x380000DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFF0x3800040x3800070x3800080x380008DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFF0x38000C0x38000CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFF0x3800100x380010DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFF0x3800140x3800170x3800180x380018DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF0x38001C0x38001CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800200x38002B0x38002C0x38002CDBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFF0x3800300x380030DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFF0x3800340x3800370x3800380x380038DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF0x38003C0x38003CDBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF0x3800400x38004B0x38004C0x38004CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFF0x3800500x3800530x3800540x380054DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFF0x3800580x380058DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFF0x38005C0x38005CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFF0x3800600x380060DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFF0x3800640x380064DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFF0x3800680x380068DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFF0x38006C0x38006CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFF0x3800700x380070DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFF0x3800740x380074DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFF0x3800780x380078DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFF0x38007C0x38007CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFF0x3800800x38008F0x3800900x380090DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFF0x3800940x38009F0x3800A00x3800A0DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFF0x3800A40x3800A70x3800A80x3800A8DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFF0x3800AC0x3800ACDBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFF0x3800B00x3800B30x3800B40x3800B4DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFF0x3800B80x3800B8DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFF0x3800BC0x3800C30x3800C40x3800C4DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFF0x3800C80x3800CB0x3800CC0x3800CCDBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFF0x3800D00x3800D0DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFF0x3800D40x3800D4DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFF0x3800D80x3800D8DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFF0x3800DC0x3800DCDBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFF0x3800E00x3800E0DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFF0x3800E40x3800E4DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFF0x3800E80x3800E8DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFF0x3800EC0x3801070x3801080x380108DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF0x38010C0x38010CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801100x3801170x3801180x380118DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF0x38011C0x38011CDBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF0x3801200x3801FF0x3802000x380200DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_00x3802040x380204DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_00x3802080x380208DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_00x38020C0x38020CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_00x3802100x380210DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_00x3802140x380214DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_00x3802180x380218DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_00x38021C0x38021CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_00x3802200x380220DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_00x3802240x3802FF0x3803000x380300DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_00x3803040x380304DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_00x3803080x380308DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_00x38030C0x38030CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_00x3803100x380310DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_00x3803140x380314DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_00x3803180x380318DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_00x38031C0x38031CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_00x3803200x380320DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_00x3803240x3803FF0x3804000x380400DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_10x3804040x380404DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_10x3804080x380408DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_10x38040C0x38040CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_10x3804100x380410DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_10x3804140x380414DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_10x3804180x380418DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_10x38041C0x38041CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_10x3804200x380420DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_10x3804240x3804FF0x3805000x380500DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_10x3805040x380504DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_10x3805080x380508DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_10x38050C0x38050CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_10x3805100x380510DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_10x3805140x380514DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_10x3805180x380518DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_10x38051C0x38051CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_10x3805200x380520DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_10x3805240x3805FF0x3806000x380600DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_20x3806040x380604DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_20x3806080x380608DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_20x38060C0x38060CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_20x3806100x380610DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_20x3806140x380614DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_20x3806180x380618DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_20x38061C0x38061CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_20x3806200x380620DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_20x3806240x3806FF0x3807000x380700DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_20x3807040x380704DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_20x3807080x380708DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_20x38070C0x38070CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_20x3807100x380710DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_20x3807140x380714DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_20x3807180x380718DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_20x38071C0x38071CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_20x3807200x380720DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_20x3807240x3807FF0x3808000x380800DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_30x3808040x380804DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_30x3808080x380808DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_30x38080C0x38080CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_30x3808100x380810DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_30x3808140x380814DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_30x3808180x380818DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_30x38081C0x38081CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_30x3808200x380820DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_30x3808240x3808FF0x3809000x380900DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_30x3809040x380904DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_30x3809080x380908DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_30x38090C0x38090CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_30x3809100x380910DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_30x3809140x380914DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_30x3809180x380918DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_30x38091C0x38091CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_30x3809200x380920DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_30x3809240x381123groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDRPF0_TYPE1_HDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr563080x0R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDRPCI-Compatible Configuration Space Header Type1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BAR0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BAR1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_DEV_ID_VEND_ID_REGTYPE1_DEV_ID_VEND_ID_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr546690x0R0xeb011e0aPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REGDevice ID and Vendor ID Register.falsefalsefalsefalseVENDOR_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54652Vendor ID.The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x1e0aRDEVICE_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54668Device ID.The Device ID register identifies the particular Function. This identifier is allocated by the vendor.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160xeb01RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_STATUS_COMMAND_REGTYPE1_STATUS_COMMAND_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr550190x4R/W0x00100000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REGStatus and Command Register.falsefalsefalsefalseIO_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IO_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54693IO Space Enable.This bit controls a Function's response to I/O Space accesses received on its primary side. - When set, the Function is enabled to decode the address and further process I/O Space accesses. - When clear, all received I/O accesses are caused to be handled as Unsupported Requests.You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar =0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: !has_io_bar ? RO : RW 000x0R/WMSEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MSE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54714Memory Space Enable.This bit controls a Function's response to Memory Space accesses received on its primary side. - When set, the Function is enabled to decode the address and further process Memory Space accesses. - When clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar =0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: !has_mem_bar ? RO : RW 110x0R/WBMEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_BME_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54732Bus Master Enable.This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction.When this bit is 0b, Memory and I/O Requests received at a RootPort must be handled as Unsupported Requests (UR)For Non-Posted Requests a Completion with UR completion status must be returned.This bit does not affect forwarding of Completions in either the Upstream or Downstream direction.The forwarding of Requests other than Memory or I/O Requests is not controlled by this bit.220x0R/WSCOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SCO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54743Special Cycle Enable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.330x0RMWI_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MWI_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54759Memory Write and Invalidate.This bit was originally described in the PCI Local Bus Specification and thePCI-to-PCI Bridge Architecture Specification. Its functionality does not applyto PCI Express. The controller hardwires this bit to 0b. For PCI Express to PCI/PCI-X Bridges, refer to the PCI Express to PCI/PCI-X Bridge Specification for requirements for this register.440x0RVGAPSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_VGAPS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54771VGA Palette Snoop.This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.550x0RPERRENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_PERREN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54782Parity Error Response.This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register.For more details see the "Error Registers" section of the PCI Express Base Specification.660x0R/WIDSELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_IDSEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54793IDSEL Stepping/Wait Cycle Control.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.770x0RSERRENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SERREN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54812SERR# Enable.When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control register. For more details see the "Error Registers" section of the PCI Express Base Specification.In addition, this bit controls transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error Messages forwarded from the secondary interface. This bit does not affect the transmission of forwarded ERR_COR messages.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54820Reserved for future use.990x0RINT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54845Interrupt Disable.Controls the ability of a Function to generate INTx emulation interrupts. When set, Functions are prevented from asserting INTx interrupts.Note: - Any INTx emulation interrupts already asserted by the Function must be deasserted when this bit is set. INTx interrupts use virtual wires that must, if asserted, be deasserted using the appropriate Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected. - For Functions that generate INTx interrupts on their own behalf, this bit is required. This bit has no effect on interrupts forwarded from the secondary side. For Functions that do not generate INTx interrupts on their own behalf this bit is optional. If this bit is not implemented, the controller hardwires it to 0b.10100x0R/WRESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54854Reserved.15110x00R--16160x0rRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54862Reserved for future use.18170x0RINT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54881Interrupt Status.When set, indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit.Setting the Interrupt Disable bit has no effect on the state of this bit.For Functions that do not generate INTx interrupts, the controller hardwiresthis bit to 0b.19190x0RCAP_LISTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54894Capabilities List.Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.20200x1RFAST_66MHZ_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5490566 MHz Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.21210x0RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54913Reserved for future use.22220x0RFAST_B2B_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54924Fast Back-to-Back Transactions Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.23230x0RMASTER_DPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54940Master Data Parity Error.This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a Poisoned Request upstreamIf the Parity Error Response bit is 0b, this bit is never set.24240x0R/W1CDEV_SEL_TIMINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54951DEVSEL Timing.This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b.26250x0RSIGNALED_TARGET_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54964Signaled Target Abort.This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side.27270x0R/W1CRCVD_TARGET_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54978Received Target Abort.This bit is set when a Requester receives a Completion with Completer AbortCompletion status. The bit is set when the Completer Abort is received by aFunction's primary side.28280x0R/W1CRCVD_MASTER_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr54991Received Master Abort.This bit is set when a Requester receives a Completion with Unsupported Request Completion status.The bit is set when the Unsupported Request is received by a Function's primary side.29290x0R/W1CSIGNALED_SYS_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55003Signaled System Error.This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR# Enable bit in the Command register is 1b.30300x0R/W1CDETECTED_PARITY_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55018Detected Parity Error.This bit is set by a Function whenever it receives a Poisoned TLP, regardlessof the state the Parity Error Response bit in the Command register. The bit isset when the Poisoned TLP is received by a Function's primary side.31310x0R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_CLASS_CODE_REV_ID_REGTYPE1_CLASS_CODE_REV_ID_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr551000x8R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REGClass Code and Revision ID Register.falsefalsefalsefalseREVISION_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55041Revision ID.The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x01RPROGRAM_INTERFACEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55061Programming Interface.This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function.Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1580x00RSUBCLASS_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55080Sub-Class Code.Specifies a base class sub-class, which identifies more specifically the operation of the Function.Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23160x00RBASE_CLASS_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55099Base Class Code.A code that broadly classifies the type of operation the Function performs.Encodings for base class, are provided in the PCI Code and ID AssignmentSpecification. All unspecified encodings are reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGTYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr552030xCR/W0x00010000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REGBIST, Header Type, Latency Timer, and Cache Line Size Register.falsefalsefalsefalseCACHE_LINE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55119Cache Line Size.The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express device behavior.700x00R/WLATENCY_MASTER_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55133Latency Timer.This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.1580x00RHEADER_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55150Header Layout.This field identifies the layout of the second part of the predefined header.The controller uses 000 0001b encoding.The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical Specification and is used in previous versions of the programming model. Careful consideration should be given to any attempt to repurpose it.22160x01RMULTI_FUNCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55170Multi-Function Device. - When set, indicates that the device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear, software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure.Except where stated otherwise, it is recommended that this bit be set if thereare multiple Functions, and clear if there is only one Function.Note: This register field is sticky.23230x0RBISTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55202BIST.This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link.Bit descriptions: - [31]: BIST Capable. When set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST. If BIST Capable is set, set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been set. Writing this bit to 0b has no effect. The controller hardwires this bit to 0b if BIST Capable is clear. - [29:28]: Reserved. - [27:24]: Completion Code. This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BAR0_REGBAR0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr553060x10R/W0x00000004PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_BAR0_REGBAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR0_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_MEM_IO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55238BAR0 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR0_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55266BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR0_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_PREFETCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55288BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR0_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR0_REG_BAR0_START_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55305BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BAR1_REGBAR1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr554030x14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_BAR1_REGBAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR1_MEM_IOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_MEM_IO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55339BAR1 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR1_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55365BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR1_PREFETCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_PREFETCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55385BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR1_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BAR1_REG_BAR1_START_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55402BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGSEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr554570x18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REGSecondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register.falsefalsefalsefalsePRIM_BUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55416Primary Bus Number.This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software.700x00R/WSEC_BUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55431Secondary Bus Number.The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge uses this register to determine when to respond to and convert a Type 1 configuration transaction on the primary interface into a Type 0 transaction on the secondary interface.1580x00R/WSUB_BUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55446Subordinate Bus Number.The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The bridge uses this register in conjunction with the Secondary Bus Number register to determine when to respond to and pass on a Type 1 configuration transaction on the primary interface to the secondary interface.23160x00R/WSEC_LAT_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55456Secondary Latency Timer.This register does not apply to PCI Express. The controller hardwires it to 00h.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.SEC_STAT_IO_LIMIT_IO_BASE_REGSEC_STAT_IO_LIMIT_IO_BASE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr557000x1CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REGSecondary Status, and I/O Limit and Base Register.The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other. If a bridge does not implement an I/O address range, then both the I/O Limit and I/O Base registers must be implemented as read-only registers that return zero when read. If a bridge supports an I/O address range, then these registers must be initialized by configuration software so default states are not specified.falsefalsefalsefalseIO_DECODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55504I/O Addressing Encode (IO Base Address)This bit encodes the IO addressing capability of the bridge.IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address decoding, the bridge assumes that the upper 16 address bits, Address[31:16], of the I/O base address (not implemented in I/O base register) are zero.Note: The bridge must still perform a full 32-bit decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case, the I/O address range supported by the bridge will be restricted to the first 64 KB of I/O Space (0000 0000h to 0000 FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Base Upper 16 Bits hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Base address. In this case, system configuration software is permitted to locate the I/O address range supported by the bridge anywhere in the 4-GB I/O Space.Note: The 4-KB alignment and granularity restrictions still apply when the bridge supports 32-bit I/O addressing.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 000x0RIO_RESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55512Reserved.310x0RIO_BASEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55525I/O Base Address.These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding, the bridge assumes that the lower 12 address bits, address[11:0], of the I/O base address (not implemented in the I/O Base register) are zero.740x0R/WIO_DECODE_BIT8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55560I/O Addressing Encode (IO Limit Address).This bit encodes the IO addressing capability of the bridge.IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address decoding, the bridge assumes that the upper 16 address bits, Address[31:16], of the I/O limit address (not implemented in I/O Limit register) are zero.Note: The bridge must still perform a full 32-bit decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case, the I/O address range supported by the bridge will be restricted to the first 64 KB of I/O Space (0000 0000h to 0000 FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Limit Upper 16 Bits hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Limit address. In this case, system configuration software is permitted to locate the I/O address range supported by the bridge anywhere in the 4-GB I/O Space.Note: The 4-KB alignment and granularity restrictions still apply when the bridge supports 32-bit I/O addressing.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 88RIO_RESERV1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55569Reserved.1190x0RIO_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55590I/O Limit Address.These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding, the bridge assumes that the lower 12 address bits, address[11:0], of the I/O limit address (not implemented in the I/O Limit register) are FFFh.The I/O Limit register can be programmed to a smaller value than the I/O Base register, if there are no I/O addresses on the secondary side of the bridge. In this case, the bridge will not forward any I/O transactions from the primary bus to the secondary and will forward all I/O transactions from the secondary bus to the primary bus.15120x0R/WSEC_STAT_RESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55599Reserved.22160x00RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55607Reserved for future use.23230x0RSEC_STAT_MDPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55624Master Data Parity Error.This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set, and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream - Port transmits a Poisoned Request DownstreamIf the Parity Error Response Enable bit is clear, this bit is never set.24240x0R/W1CRSVDP_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55632Reserved for future use.26250x0RSEC_STAT_SIG_TRGT_ABRTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55646Signaled Target Abort.This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error.27270x0R/W1CSEC_STAT_RCVD_TRGT_ABRTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55660Received Target Abort.This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status.28280x0R/W1CSEC_STAT_RCVD_MSTR_ABRTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55674Received Master Abort.This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status.29290x0R/W1CSEC_STAT_RCVD_SYS_ERRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55686Received System Error.This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message.30300x0R/W1CSEC_STAT_DPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55699Detected Parity Error.This bit is set by a Function when a Poisoned TLP is received by its secondary side, regardless of the state the Parity Error Response Enable bit in the Bridge Control register.31310x0R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.MEM_LIMIT_MEM_BASE_REGMEM_LIMIT_MEM_BASE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr557580x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REGMemory Limit and Base Register.The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there is no prefetchable memory space, and there is no memory-mapped space on the secondary side of the bridge, then the bridge will not forward any memory transactions from the primary bus to the secondary bus and will forward all memory transactions from the secondary bus to the primary bus.falsefalsefalsefalseMEM_BASE_RESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55720Reserved.300x0RMEM_BASEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55732Memory Base Address.These bits correspond to the upper 12 address bits, Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the lower 20 address bits, Address[19:0], of the memory base address (not implemented in the Memory Base register) are zero.1540x000R/WMEM_LIMIT_RESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55740Reserved.19160x0RMEM_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55757Memory Limit Address.These bits correspond to the upper 12 address bits, Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the lower 20 address bits, Address[19:0], of the memory limit address (not implemented in the Memory Limit register) are F FFFFh.The Memory Limit register must be programmed to a smaller value than the Memory Base register if there is no memory-mapped address space on the secondary side of the bridge.31200x000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_MEM_LIMIT_PREF_MEM_BASE_REGPREF_MEM_LIMIT_PREF_MEM_BASE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr558830x24R/W0x00010001PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REGPrefetchable Memory Limit and Base Register.The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported, as defined in PCI-to-PCI Bridge Architecture Specification. The Prefetchable Memory Limit and Prefetchable Memory Base registers are optional. They define a prefetchable memory address range which is used by the bridge to determine when to forward memory transactions from one interface to the other (see the PCI-to-PCI Bridge Architecture Specification for additional details).falsefalsefalsefalsePREF_MEM_DECODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55799Prefetchable Memory Base Decode.This bit encodes whether or not the bridge supports 64-bitaddresses.Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable memory address range, or if there is no prefetchable memory address range, then the configuration parameter MEM_DECODE_64_0 must be changed to 0.The value of PREF_MEM_DECODE indicates the following: - 0b: Indicates that the bridge supports only 32 bit addresses. - 1b: Indicates that the bridge supports 64 bit addresses. Prefetchable Base Upper 32 Bits registers holds the rest of the 64-bit prefetchable base address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.000x1RPREF_RESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55808Reserved.310x0RPREF_MEM_BASEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55829Prefetchable Memory Base Address.If the Prefetchable Memory Base register indicates support for 32-bit addressing, then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read.If the Prefetchable Memory Base register indicates support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read/write register which must be initialized by configuration software.If a 64-bit prefetchable memory address range is supported, the Prefetchable Base Upper 32 Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address range.1540x000R/WPREF_MEM_LIMIT_DECODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55852Prefetchable Memory Limit Decode.This bit encodes whether or not the bridge supports 64-bitaddresses.Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit.The value of PREF_MEM_LIMIT_DECODE indicates the following: -0b: Indicates that the bridge supports only 32 bit addresses. -1b: Indicates that the bridge supports 64 bit addresses. Prefetchable Limit Upper 32 Bits registers holds the rest of the 64-bit prefetchable limit address.16160x1RPREF_RESERV1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55860Reserved.19170x0RPREF_MEM_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55882Prefetchable Memory Limit Address.If the Prefetchable Memory Limit register indicates support for 32-bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read.If the Prefetchable Memory Limit registers indicate support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read/write register which must be initialized by configuration software.If a 64-bit prefetchable memory address range is supported, the Prefetchable Limit Upper 32 Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit limit addresses which specify the prefetchable memory address range.31200x000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_BASE_UPPER_REGPREF_BASE_UPPER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr559120x28R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_PREF_BASE_UPPER_REGPrefetchable Base Upper 32 Bits Register.The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register.falsefalsefalsefalsePREF_MEM_BASE_UPPERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55911Prefetchable Base Upper 32 Bit.If the Prefetchable Memory Base register indicates support for 32-bit addressing, then this register is implemented as read-only register that returns zero when read.If the Prefetchable Memory Base register indicate support for 64-bit addressing, then this register is implemented as read/write register which must be initialized by configuration software.This register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address range.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PREF_MEM_LIMIT_PREF_MEM_BASE_REG.PREF_MEM_DECODE ? RW : RO 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.PREF_LIMIT_UPPER_REGPREF_LIMIT_UPPER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr559380x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REGPrefetchable Limit Upper 32 Bits Register.The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register.falsefalsefalsefalsePREF_MEM_LIMIT_UPPERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55937Prefetchable Limit Upper 32 Bit.If the Prefetchable Memory Limit register indicate support for 64-bit addressing, then this register is implemented as read/write register which must be initialized by configuration software.This register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address range.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PREF_MEM_LIMIT_PREF_MEM_BASE_REG.PREF_MEM_DECODE ? RW : RO 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.IO_LIMIT_UPPER_IO_BASE_UPPER_REGIO_LIMIT_UPPER_IO_BASE_UPPER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr559920x30R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REGI/O Limit and Base Upper 16 Bits Register.The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers.falsefalsefalsefalseIO_BASE_UPPERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55968I/O Base Upper 16 Bits.If the I/O Base register indicates support for 16-bit I/O address decoding, then this register is implemented as a read-only register which return zero when read.If the I/O base register indicates support for 32-bit I/O addressing, then this register must be initialized by configuration software.If 32-bit I/O address decoding is supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the 32-bit base address, that specify the I/O address range. See the PCI-to-PCI Bridge Architecture Specification for additional details.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: SEC_STAT_IO_LIMIT_IO_BASE_REG.IO_DECODE ? RW : RO 1500x0000RIO_LIMIT_UPPERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr55991I/O Limit Upper 16 Bits.If the I/O Limit register indicates support for 16-bit I/O address decoding, then this register is implemented as a read-only register which return zero when read.If the I/O Limit register indicates support for 32-bit I/O addressing, then this register must be initialized by configuration software.If 32-bit I/O address decoding is supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the 32-bit limit address, that specify the I/O address range. See the PCI-to-PCI Bridge Architecture Specification for additional details).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: SEC_STAT_IO_LIMIT_IO_BASE_REG.IO_DECODE ? RW : RO 31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_CAP_PTR_REGTYPE1_CAP_PTR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr560290x34R0x00000040PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REGCapabilities Pointer Register.falsefalsefalsefalseCAP_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_CAP_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56021Capabilities Pointer.This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure, this register must point to a valid capability structure and either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are Reserved and must be set to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x40RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_CAP_PTR_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56028Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.TYPE1_EXP_ROM_BASE_REGTYPE1_EXP_ROM_BASE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr560920x38R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REGExpansion ROM Base Address Register.This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.falsefalsefalsefalseROM_BAR_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56062Expansion ROM Enable.This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b, the Function's expansion ROM address space is disabled. When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register. The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56070Reserved for future use.1010x000REXP_ROM_BASE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56091Expansion ROM Base Address.Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 31110x000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TYPE1_HDR.BRIDGE_CTRL_INT_PIN_INT_LINE_REGBRIDGE_CTRL_INT_PIN_INT_LINE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr563070x3CR/W0x000001ffPE0_DWC_pcie_ctl_DBI_Slave_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REGBridge Control, Interrupt Pin, and Interrupt Line Register.falsefalsefalsefalseINT_LINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56110Interrupt Line.The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.700xffR/WINT_PINPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56146Interrupt PIN.The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses.Valid values are: - 01h, 02h, 03h, and 04h: map to legacy interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: indicates that the Function uses no legacy interrupt Message(s). - 05h through FFh: Reserved.PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth.For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x01RPEREPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56156Parity Error Response Enable.This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register.16160x0R/WSERR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56165SERR# Enable.This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL from secondary to primary.17170x0R/WISA_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56190ISA Enable.Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions will be forwarded if they address the last 768 bytes in each 1-KB block.The following actions are taken based on the value of the ISA_EN bit: - 0b: Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit registers - 1b: Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1-KB block.18180x0R/WVGA_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56240VGA Enable.Modifies the response by the bridge to VGA compatible addresses.If the VGA Enable bit is set, the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and, conversely, block the forwarding of these addresses from the secondary to primary interface): - Memory accesses in the range 000A 0000h to 000B FFFFh - I/O addresses in the first 64 KB of the I/O address space (Address[31:16] are 0000h) where Address[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases determined by the setting of VGA 16-bit Decode )If the VGA Enable bit is set, forwarding of these accesses is independent of the I/O address range and memory address ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the Prefetchable Memory Base and Limit registers of the bridge. (Forwarding of these accesses is also independent of the setting of the ISA Enable bit (in the Bridge Control register) when the VGA Enable bit is set. Forwarding of these accesses is qualified by the I/O Space Enable and Memory Space Enable bits in the Command register.)The following actions are taken based on the value of the VGA_EN bit: - 0b: Do not forward VGA compatible memory and I/O addresses from the primary to the secondary interface (addresses defined above) unless they are enabled for forwarding by the defined I/O and memory address ranges - 1b: Forward VGA compatible memory and I/O addresses (addresses defined above) from the primary interface to the secondary interface (if the I/O Space Enable and Memory Space Enable bits are set) independent of the I/O and memory address ranges and independent of the ISA Enable bitFor Functions that do not support VGA, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 19190x0RVGA_16B_DECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56263VGA 16 bit decode.This bit only has meaning if VGA Enable bit is set.This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary to secondary.The following actions are taken based on the value of the VGA_16B_DEC bit: - 0b: Execute 10-bit address decodes on VGA I/O accesses - 1b: Execute 16-bit address decodes on VGA I/O accessesFor Functions that do not support VGA, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 20200x0RMSTR_ABORT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56281Master Abort Mode.This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21210x0RSBRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56298Secondary Bus Reset.Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor first-access-following-reset timing requirements, unless the Readiness Notifications mechanism is used or if the Immediate Readiness bit in the relevant Function's Status Register register is set.Port configuration registers must not be changed, except as required to update Port status.22220x0R/WBRIDGE_CTRL_RESERVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TYPE1_HDR_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56306Reserved.31230x000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAPPF0_PM_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr566940x40R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PM_CAPPF PCI Power Management Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CON_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGCAP_ID_NXT_PTR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr565000x0R0x03c35001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PM_CAP_CAP_ID_NXT_PTR_REGPower Management Capabilities Register.falsefalsefalsefalsePM_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56327Capability ID.This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h.700x01RPM_NEXT_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56344Next Capability Pointer.This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list, this field is set to 00h.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x50RPM_SPEC_VERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56361Version.This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0>.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.18160x3RPME_CLKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56372PME Clock.Does not apply to PCI Express, the controller hardwires it to 0b.Note: This register field is sticky.19190x0R--20200x0rDSIPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56391Device Specific Initialization.The DSI bit indicates whether special initialization of this function is required.When set, indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized state.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x0RAUX_CURRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56424Aux_Current.This 3 bit field reports the Vaux auxiliary current requirements for the function.If this function implements the Data Register, the controller hardwires this field to 000b.If PME_Support is 0 xxxxb (PME assertion from D3cold is not supported), the controller hardwires this field to 0000b.For functions where PME_Support is 1 xxxxb (PME assertion from D3cold is supported), and which do not implement the Data field, the following encodings apply: - b111 375mA Vaux Max. Current Required - b110 320mA Vaux Max. Current Required - b101 270mA Vaux Max. Current Required - b100 220mA Vaux Max. Current Required - b011 160mA Vaux Max. Current Required - b010 100mA Vaux Max. Current Required - b001 55mA Vaux Max. Current Required - b000 0 self poweredNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.24220x7RD1_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56440D1_Support.If this bit is set, this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RD2_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56456D2_Support.If this bit is set, this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26260x0RPME_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56499PME_Support.This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages.A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. - bit(27) X XXX1b - PME can be generated from D0 - bit(28) X XX1Xb - PME can be generated from D1 - bit(29) X X1XXb - PME can be generated from D2 - bit(30) X 1XXXb - PME can be generated from D3hot - bit(31) 1 XXXXb - PME can be generated from D3coldBit 31 (PME can be asserted from D3cold) represents a special case. Functions that set this bit require some sort of auxiliary power source. Implementation specific mechanisms are recommended to validate that the power source is available before setting this bit.Each bit that corresponds to a supported D-state must be set for PCI-PCI Bridge structures representing Ports on Root Complexes/Switches to indicate that the Bridge will forward PME Messages. Bit 31 must only be set if the Port is still able to forward PME Messages when main power is not available.The read value from this field is the write value && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are fields in this register.The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3127RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PM_CAP.CON_STATUS_REGCON_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr566930x4R/W0x00000008PE0_DWC_pcie_ctl_DBI_Slave_PF0_PM_CAP_CON_STATUS_REGPower Management Control and Status Register.This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs.falsefalsefalsefalsePOWER_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56544PowerState.This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below.You can write to this register; however, the read-back value is the actual power state, not the write value. If you attempt to write an unsupported, optional state to this field, the write operation completes normally; however, the data is discarded and no state change occurs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 10R/WfalsetruefalseD00x0D0 power stateD10x1D1 power stateD20x2D2 power stateD3hot0x3D3hot D3hot power stateRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56552Reserved for future use.220x0RNO_SOFT_RSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56578No_Soft_Reset.This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set, this transition preserves internal function state. The function is in D0Active and no additional software intervention is required. - When clear, this transition results in undefined internal function state.Regardless of this bit, functions that transition from D3hot to D0 by Fundamental Reset will return to D0Uninitialized with only PME context preserved if PME is supported and enabled.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.330x1RRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56586Reserved for future use.740x0RPME_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56607PME_En. - When set, the function is permitted to generate a PME. - When clear, the function is not permitted to generate a PME.If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is available this bit is RWS and the bit is not modified by Conventional Reset or FLR.If PME_Support is 0 xxxxb, this field is not sticky (RW).If PME_Support is 0 0000b, the controller hardwires this bit to 0b.Note: This register field is sticky.88R/WDATA_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56619Data_Select.This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented, this field must be hardwired to 0000b.1290x0RDATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56633Data_Scale.This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details, see 7.5.2.3 section of PCI Express Base Specification.14130x0RPME_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56652PME_Status.This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit.If PME_Support bit 31 of the Power Management Capabilities register is clear, this bit is permitted to be hardwired to 0b.Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this register value is not modified by Conventional Reset or FLR.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56660Reserved for future use.21160x00RB2_B3_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56670B2B3 Support for D3hot.For a description of this standard PCIe register field, see the PCI Express Base Specification.22220x0RBUS_PWR_CLK_CON_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56680Bus Power/Clock Control Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.23230x0RDATA_REG_ADD_INFOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56692Data.This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field.31240x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAPPF0_MSI_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr570890x50R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAPPF MSI Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr568720x0R/W0x038a7005PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REGMSI Capability Header and Message Control Register.falsefalsefalsefalsePCI_MSI_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56712Capability ID.Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure.700x05RPCI_MSI_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56729Next Capability Pointer.This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x70RPCI_MSI_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56746MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear, the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function's service request. For more details on control of INTx interrupts, see section 7.5.1.1 of PCI Express Base Specification. - If clear, the function is prohibited from using MSI to request service.16160x0R/WPCI_MSI_MULTIPLE_MSG_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56772Multiple Message Capable.System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors, it requests four by initializing this field to 010b). The encoding is defined as: - 000b: 1 vector requested - 001b: 2 vectors requested - 010b: 4 vectors requested - 011b: 8 vectors requested - 100b: 16 vectors requested - 101b: 32 vectors requested - 110b: Reserved - 111b: ReservedNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19170x5RPCI_MSI_MULTIPLE_MSG_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56797Multiple Message Enable.Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a function requests four vectors (indicated by a Multiple Message Capable encoding of 010b), system software can allocate either four, two, or one vector by writing a 010b, 001b, or 000b to this field, respectively. When MSI is enabled, a function will be allocated at least 1 vector. The encoding is defined as: - 000b: 1 vector allocated - 001b: 2 vectors allocated - 010b: 4 vectors allocated - 011b: 8 vectors allocated - 100b: 16 vectors allocated - 101b: 32 vectors allocated - 110b: Reserved - 111b: Reserved22200x0R/WPCI_MSI_64_BIT_ADDR_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5681764 bit address capable. - If set, the function is capable of sending a 64-bit message address. - If clear, the function is not capable of sending a 64-bit message address.This bit must be set if the function is a PCI Express Endpoint.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.23230x1RPCI_PVM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56830Per-Vector Masking Capable. - If set, the function supports MSI Per-Vector Masking. - If clear, the function does not support MSI Per-Vector Masking.This bit must be set if the function is a PF or VF within an SR-IOV Device.24240x1RPCI_MSI_EXT_DATA_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56847Extended Message Data Capable. - If set, the function is capable of providing Extended Message Data. - If clear, the function does not support providing Extended Message Data.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RPCI_MSI_EXT_DATA_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56863Extended Message Data Enable. - If set, the function is enabled to provide Extended Message Data. - If clear, the function is not enabled to provide Extended Message Data.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO 26260x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56871Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGMSI_CAP_OFF_04H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr569000x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_04H_REGMessage Address Register for MSI (Offset 04h).falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56883Reserved for future use.100x0RPCI_MSI_CAP_OFF_04HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56899Message Address - System-specified message address.If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set, the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI transaction. Address[1:0] are set to 00b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3120x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGMSI_CAP_OFF_08H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr569790x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_08H_REGFor a function that supports a 32-bit message address, - bits[31:16] of this register represent the Extended Message Data, and - bits[15:0] of this register represent the Message DataFor a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.falsefalsefalsefalsePCI_MSI_CAP_OFF_08HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56950For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.For a function that supports a 64-bit message address, it contains lower 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0AHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr56978For a function that supports a 32-bit message address, this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is outside the MSI Capability structure and undefined. For the MSI Capability structures with Per-vector Masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is RsvdP. If the Extended Message Data Enable bit (bit 26 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the DWORD Memory Write transaction uses Extended Message Data for the upper 16 bits; otherwise, it uses 0000h for the upper 16 bits.For a function that supports a 64-bit message address, it contains upper 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGMSI_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr570430xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REGFor a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains Message Data.falsefalsefalsefalsePCI_MSI_CAP_OFF_0CHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57022For a function that supports a 32-bit message address, this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0EHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57042For a function that supports a 32-bit message address, this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGMSI_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr570720x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_10H_REGFor a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_10HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57071Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit, contains Mask Bits.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGMSI_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr570880x14R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_14H_REGPending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_14HPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57087Pending Bits. For each pending bit that is set, the function has a pending associated message.3100x00000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAPPF0_PCIE_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr604530x70R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAPPF PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUSregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr572460x0R0x0002b010PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCI Express Capabilities, ID, Next Pointer Register.falsefalsefalsefalsePCIE_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57107Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure.700x10RPCIE_CAP_NEXT_PTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57122Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580xb0RPCIE_CAP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57146Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number.A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example, through a new Capability field) is permitted to increment this field. All such changes to the PCI Express Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as functions reporting any such Capability Version numbers will contain a PCI Express Capability structure that is compatible with that piece of software.The controller hardwires this field to 2h for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.Note: This register field is sticky.19160x2RPCIE_DEV_PORT_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57173Device/Port Type. Indicates the specific type of this PCI Express function.Note: Different functions in a Multi-Function Device can generally be of different types.Defined encodings for functions that implement a Type 00h PCI Configuration Space header are: - 0000b PCI Express Endpoint - 0001b Legacy PCI Express EndpointDefined encodings for functions that implement a Type 01h PCI Configuration Space header are: - 0100b Root Port of PCI Express Root Complex - 0101b Upstream Port of PCI Express Switch - 0110b Downstream Port of PCI Express SwitchAll other encodings are Reserved.Note: Different Endpoint types have notably different requirements in Section 1.3.2 of PCI Express Base Specification regarding I/O resources, Extended Configuration Space, and other capabilities.2320RPCIE_SLOT_IMPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57189Slot Implemented. When set, this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit is undefined for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 24240x0RPCIE_INT_MSG_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57231PCIE Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Base Specification.Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this Capability structure.For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register.For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant.If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.29250x00RRSVDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57238Reserved.30300x0RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57245Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGDEVICE_CAPABILITIES_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr573940x4R0x00008021PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REGDevice Capabilities Register.The Device Capabilities register identifies PCI Express device function specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_PAYLOAD_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57278Max_Payload_Size Supported.This field indicates the maximum payload size that the function can support for TLPs.Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedThe functions of a Multi-Function Device are permitted to report different values for this field.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x1RPCIE_CAP_PHANTOM_FUNC_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57332Phantom Functions Supported.This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the Tag identifier (see Section 2.2.6.2 of PCI Express Base Specification for a description of Tag Extensions).With every Function in an ARI Device, the Phantom Functions Supported field must be set to 00b. The remainder of this field description applies only to non-ARI Multi-Function Devices.This field indicates the number of most significant bits of the Function Number portion of Requester ID that are logically combined with the Tag identifier.Defined encodings are: - 00b: No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. - 01b: The most significant bit of the Function number in Requester ID is used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. - 10b: The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as Phantom Functions. - 11b: All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single Function 0 that is permitted to use all other Function Numbers as Phantom Functions.Note: Phantom Function support for the function must be enabled by the Phantom Functions Enable field in the Device Control register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.430x0RPCIE_CAP_EXT_TAG_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57359Extended Tag Field Supported.This bit, in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register, indicates the maximum supported size of the Tag field as a Requester. This bit must be set if the 10-Bit Tag Requester Supported bit is set.Defined encodings are: - 0b: 5-bit Tag field supported - 1b: 8-bit Tag field supportedNote: 8-bit Tag field generation must be enabled by the Extended Tag Field Enable bit in the Device Control register of the Requester Function before 8-bit Tags can be generated by the Requester. See Section 2.2.6.2 of PCI Express Base Specificationfor interactions with enabling the use of 10-Bit Tags.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.550x1RRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57366Reserved for future use.1460x000RPCIE_CAP_ROLE_BASED_ERR_REPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57386Role-Based Error Reporting. When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.15150x1RRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57393Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSDEVICE_CONTROL_DEVICE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr577390x8R/W0x00002010PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUSDevice Control and Device Status Register.This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters.falsefalsefalsefalsePCIE_CAP_CORR_ERR_REPORT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57417Correctable Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_COR Messages (for more details, see section 6.2.5, section 6.2.6, and section 6.2.10.2 of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR Message is generated.000x0R/WPCIE_CAP_NON_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57434Non-Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages (for more details, see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each function from point-of-view of the respective Function.For a Root Port, the reporting of Non-fatal errors is internal to the root. No external ERR_NONFATAL Message is generated.110x0R/WPCIE_CAP_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57450Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_FATAL Messages (for more details, see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of Fatal errors is internal to the root. No external ERR_FATAL Message is generated.220x0R/WPCIE_CAP_UNSUPPORT_REQ_REP_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57464Unsupported Request Reporting Enable.This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (for more details, see section 6.2.5 and section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each Function from point-of-view of the respective Function.330x0R/WPCIE_CAP_EN_REL_ORDERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57484Enable Relaxed Ordering.If this bit is set, the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details, see section 2.2.6.4 and section 2.4 of PCI Express Base Specification).For a function that never sets the Relaxed Ordering attribute in transactions it initiates as a Requester, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x1R/WPCIE_CAP_MAX_PAYLOAD_SIZE_CSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57521Max_Payload_Size.This field sets maximum TLP payload size for the Function. As a Receiver, the Function must handle TLPs as large as the set value. As a Transmitter, the Function must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities (DEVICE_CAPABILITIES_REG) register (for more details, see section 7.5.3.3 of PCI Express Base Specification).Defined encodings for this field are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedFor Functions that support only the 128-byte max payload size, the controller hardwires this field to 000b.System software is not required to program the same value for this field for all the Functions of a Multi-Function device (for more details, see section 2.2.2 of PCI Express Base Specification).For ARI Devices, Max_Payload_Size is determined solely by the setting in Function0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.750x0R/WPCIE_CAP_EXT_TAG_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57553Extended Tag Field Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If the Extended Tag Field Enable bit is set, the function is permitted to use an 8-bit Tag field as a Requester - If the Extended Tag Field Enable bit is clear, the Function is restricted to a 5-bit Tag fieldSee section 2.2.6.2 of PCI Express Base Specification for required behavior when the 10-Bit Tag Requester Enable bit is set.If software changes the value of the Extended Tag Field Enable bit while the function has outstanding Non-Posted Requests, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO 88R/WPCIE_CAP_PHANTOM_FUNC_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57587Phantom Functions Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If this bit is set, it enables a function to use unclaimed functions as Phantom functions to extend the number of outstanding transaction identifiers - If this bit is clear, the function is not allowed to use Phantom functionsFor more details, see section 2.2.6.2 of PCI Express Base Specification.Software should not change the value of this bit while the function has outstanding Non-Posted Requests; otherwise, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO 99RPCIE_CAP_AUX_POWER_PM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57614Aux Power PM Enable.This bit is derived by sampling the sys_aux_pwr_det input.When set this bit, enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems should continue to indicate PME Aux power requirements. Aux power is allocated as requested in the Aux_Current field of the Power Management Capabilities register (PMC), independent of the PME_En bit in the Power Management Control/Status register (PMCSR). For Multi-Function devices, a component is allowed to draw Aux power if at least one of the functions has this bit set.Note: Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this bit is not modified by Conventional Reset.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: This register field is sticky.1010R/WPCIE_CAP_EN_NO_SNOOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57641Enable No Snoop.If this bit is set, the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express Base Specification).Note: Setting this bit to 1b should not cause a function to set the No Snoop attribute on all transactions that it initiates. Even when this bit is set, a function is only permitted to set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system.The controller hardwires this bit 0b if a function would never set the No Snoop attribute in transactions it initiates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 11110x0RPCIE_CAP_MAX_READ_REQ_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57664Max_Read_Request_Size.This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: - 000b: 128 bytes maximum Read Request size - 001b: 256 bytes maximum Read Request size - 010b: 512 bytes maximum Read Request size - 011b: 1024 bytes maximum Read Request size - 100b: 2048 bytes maximum Read Request size - 101b: 4096 bytes maximum Read Request size - 110b: Reserved - 111b: ReservedFor functions that do not generate Read Requests larger than 128 bytes and functions that do not generate Read Requests on their own behalf, the controller implements this field as Read Only (RO) with a value of 000b.14120x2R/W--16150x0rPCIE_CAP_NON_FATAL_ERR_DETECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57682Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.17170x0R/W1C--18180x0rPCIE_CAP_UNSUPPORTED_REQ_DETECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57697Unsupported Request Detected.This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function Device, each function indicates status of errors as perceived by the respective function.19190x0R/W1CPCIE_CAP_AUX_POWER_DETECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57710AUX Power Detected.Functions that require Aux power report this bit as set if Aux power is detected by the function.This bit is derived by sampling the sys_aux_pwr_det input.2020RPCIE_CAP_TRANS_PENDINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57730Transactions Pending.Endpoints:When set, this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.Root and Switch Ports:The controller hardwires this bit to 0b.21210x0RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57738Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGLINK_CAPABILITIES_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr580940xCR0x00780c84PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES_REGLink Capabilities Register.The Link Capabilities register identifies PCI Express Link specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_LINK_SPEEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57779Max Link Speed.This field indicates the maximum Link speed of the associated Port.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are reserved.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x4RPCIE_CAP_MAX_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57815Maximum Link Width.This field indicates the maximum Link width (xN – corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width.Defined encodings are: - 00 0001b x1 - 00 0010b x2 - 00 0100b x4 - 00 1000b x8 - 00 1100b x12 - 01 0000b x16 - 10 0000b x32All other encodings are Reserved.Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.For a description of this standard PCIe register field, see the PCI Express Base Specification.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.940x08RPCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57840Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification.Defined encodings are: - 00b: No ASPM Support - 01b: L0s Supported - 10b: L1 Supported - 11b: L0s and L1 SupportedMulti-Function devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.11100x3RPCIE_CAP_L0S_EXIT_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57898L0s Exit Latency.This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; however, see the Implementation Note "Potential Issues With Legacy Software When L0s is Not Supported" in section 5.4.1.1 of PCI Express Base Specification for the recommended value.Defined encodings are: - 000b: Less than 64 ns - 001b: 64 ns to less than 128 ns - 010b: 128 ns to less than 256 ns - 011b: 256 ns to less than 512 ns - 100b: 512 ns to less than 1 us - 101b: 1 us to less than 2 us - 110b: 2 us to 4 us - 111b: More than 4 usNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1412RPCIE_CAP_L1_EXIT_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57952L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined.Defined encodings are: - 000b: Less than 1us - 001b: 1 us to less than 2 us - 010b: 2 us to less than 4 us - 011b: 4 us to less than 8 us - 100b: 8 us to less than 16 us - 101b: 16 us to less than 32 us - 110b: 32 us to 64 us - 111b: More than 64 μsNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1715RPCIE_CAP_CLOCK_POWER_MANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr57986Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.For Downstream Ports, the controller hardwires this bit to 0b.Note: This register field is sticky.1818RPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58006Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19190x1RPCIE_CAP_DLL_ACTIVE_REP_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58025Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.20200x1RPCIE_CAP_LINK_BW_NOT_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58051Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x1RPCIE_CAP_ASPM_OPT_COMPLIANCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58070ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 22220x1RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58077Reserved for future use.23230x0RPCIE_CAP_PORT_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58093Port Number. This field indicates the PCI Express Port number for the given PCI Express Link.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGLINK_CONTROL_LINK_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr586350x10R/W0x10000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REGLink Control and Link Status Register.This register controls and provides information about PCI Express Link specific parameters.falsefalsefalsefalsePCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58144Active State Power Management (ASPM) Control.This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to enable ASPM.Defined encodings are: - 00b: Disabled - 01b: L0s Entry Enabled - 10b: L1 Entry Enabled - 11b: L0s and L1 Entry EnabledNote: "L0s Entry Enabled" enables the Transmitter to enter L0s. If L0s is supported, the Receiver must be capable of entering L0s even when the Transmitter is disabled from entering L0s (00b or 10b).ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link. When disabling ASPM L1, software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link. ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1.For Multi-Function Devices (including ARI Devices), it is recommended that software program the same value for this field in all Functions. For non-ARI Multi-Function Devices, only capabilities enabled in all Functions are enabled for the component as a whole.For ARI Devices, ASPM Control is determined solely by the setting in Function0, regardless of Function 0's D-state. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise, the result is undefined.100x0R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58152Reserved for future use.220x0RPCIE_CAP_RCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58194Read Completion Boundary (RCB).Root Ports:Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b: 64 byte - 1b: 128 byteThe controller hardwires this bit for a Root Port and returns its RCB support capabilities.Endpoints and Bridges:Optionally set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Refer to Section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b 64 byte - 1b 128 byteConfiguration software must only set this bit if the Root Port Upstream from the Endpoint or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion Boundary bit).For functions that do not implement this feature, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 330x0RPCIE_CAP_LINK_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58222Link Disable.This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.After clearing this bit, software must honor timing requirements defined in Section 6.6.1 with respect to the first Configuration Read following a Conventional Reset.In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO 44R/WPCIE_CAP_RETRAIN_LINKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58253Retrain Link.A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. If the Port is in DPC when a write of 1b to this bit occurs, the result is undefined. Reads of this bit always return 0b.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.This bit is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.This bit always returns 0b when read.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description 55R/WPCIE_CAP_COMMON_CLK_CONFIGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58288Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.For non-ARI Multi-Function Devices, software must program the same value for this bit in all Functions. If not all Functions are Set, then the component must as a whole assume that its reference clock is not common with the Upstream component.For ARI Devices, Common Clock Configuration is determined solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies.After changing the value in this bit in both components on a Link, software must trigger the Link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port.660x0R/WPCIE_CAP_EXTENDED_SYNCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58307Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI Express Base Specification). This mode provides external devices (for example, logic analyzers) monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication.For Multi-Function devices if any function has this bit set, then the component must transmit the additional Ordered Sets when exiting L0s or when in Recovery.770x0R/WPCIE_CAP_EN_CLK_POWER_MANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58351Enable Clock Power Management.Applicable only for Upstream Ports and with form factors that support a "Clock Request" (CLKREQ#) mechanism, this bit operates as follows: - 0b: Clock power management is disabled and device must hold CLKREQ# signal low. - 1b: When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according to protocol defined in appropriate form factor specification.For a non-ARI Multi-Function Device, power-management-configuration software must only Set this bit if all Functions of the Multi-Function Device indicate a 1b in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage Link clock only if this bit is Set for all Functions.For ARI Devices, Clock Power Management is enabled solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.The CLKREQ# signal may also be controlled via the L1 PM Substates mechanism. Such control is not affected by the setting of this bit.For Downstream Ports and components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities register), the controller hardwires this bit to 0b.The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This register field is sticky.88R/WPCIE_CAP_HW_AUTO_WIDTH_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58374Hardware Autonomous Width Disable.When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.For components that do not implement the ability autonomously to change Link width, the ciontroller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WPCIE_CAP_LINK_BW_MAN_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58398Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1010R/WPCIE_CAP_LINK_AUTO_BW_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58422Link Autonomous Bandwidth Management Interrupt Enable.When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1111R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58430Reserved for future use.13120x0RPCIE_CAP_DRS_SIGNALING_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58469DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b: DRS not ReportedIf DRS Supported is set, receiving a DRS Message will set DRS Message Received in the Link Status 2 Register but will otherwise have no effect - 01b: DRS Interrupt EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, and either MSI or MSI-X is enabled, an MSI or MSI-X interrupt is generated using the vector in Interrupt Message Number (section 7.5.3.2) - 10b: DRS to FRS Signaling EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, the Port must send an FRS Message Upstream with the FRS Reason field set to DRS Message Received.Behavior is undefined if this field is set to 10b and the FRS Supported bit in the Device Capabilities 2 Register is Clear.Behavior is undefined if this field is set to 11b.For Downstream Ports with the DRS Supported bit clear in the Link Capabilities 2 register, the controller hardwires this field to 00b.This field is Reserved for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES2_REG.DRS_SUPPORTED ? RW : RO 15140x0R/WPCIE_CAP_LINK_SPEEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58494Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.The value in this field is undefined when the Link is not up.1916RPCIE_CAP_NEGO_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58514Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link.Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32All other encodings are Reserved. The value in this field is undefined when the Link is not up.2520RRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58522Reserved for future use.26260x0RPCIE_CAP_LINK_TRAININGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58539Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and the controller hardwires it to 0b.2727RPCIE_CAP_SLOT_CLK_CONFIGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58559Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear.For a Multi-Function Device, each Function must report the same value for this bit.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 28280x1RPCIE_CAP_DLL_ACTIVEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58575Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.This bit must be implemented if the Data Link Layer Link Active Reporting Capable bit is 1b. Otherwise, the controller hardwires it to 0b.2929RPCIE_CAP_LINK_BW_MAN_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58608Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of 1b to the Retrain Link bit.Note: This bit is set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason. - Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.The default value of this bit is 0b.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.3030R/W1CPCIE_CAP_LINK_AUTO_BW_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58634Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.3131R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.SLOT_CAPABILITIES_REGSLOT_CAPABILITIES_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr588500x14R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_SLOT_CAPABILITIES_REGSlot Capabilities Register.The Slot Capabilities register identifies PCI Express slot specific capabilities.falsefalsefalsefalsePCIE_CAP_ATTENTION_INDICATOR_BUTTONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58655Attention Button Present. When set, this bit indicates that an Attention Button for this slot is electrically controlled by the chassis.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 000x0RPCIE_CAP_POWER_CONTROLLERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58670Power Controller Present. When set, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 110x0RPCIE_CAP_MRL_SENSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58683MRL Sensor Present. When set, this bit indicates that an MRL Sensor is implemented on the chassis for this slot.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 220x0RPCIE_CAP_ATTENTION_INDICATORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58697Attention Indicator Present. When set, this bit indicates that an Attention Indicator is electrically controlled by the chassis.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 330x0RPCIE_CAP_POWER_INDICATORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58711Power Indicator Present. When set, this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 440x0RPCIE_CAP_HOT_PLUG_SURPRISEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58728Hot-Plug Surprise. When set, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow for such removal without impacting continued software operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 550x0RPCIE_CAP_HOT_PLUG_CAPABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58741Hot-Plug Capable. When set, this bit indicates that this slot is capable of supporting hot-plug operations.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 660x0RPCIE_CAP_SLOT_POWER_LIMIT_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58773Slot Power Limit Value. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot (for more detais, see Section 6.9 of PCI Express Base Specification) or by other means to the adapter.Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field except when the Slot Power Limit Scale field equals 00b (1.0x) and Slot Power Limit Value exceeds EFh, the following alternative encodings are used: - F0h: 250 W Slot Power Limit - F1h: 275 W Slot Power Limit - F2h: 300 W Slot Power Limit - F3h - FFh: Reserved for Slot Power Limit values above 300 WThis register must be implemented if the Slot Implemented bit is set.Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message.The default value prior to hardware/firmware initialization is 0000 0000b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 1470x00RPCIE_CAP_SLOT_POWER_LIMIT_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58798Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details, see Section 6.9 of PCI Express Base Specification).Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001xThis register must be implemented if the Slot Implemented bit is set.Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message.The default value prior to hardware/firmware initialization is 00b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 16150x0RPCIE_CAP_ELECTROMECH_INTERLOCKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58812Electromechanical Interlock Present. When set, this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 17170x0RPCIE_CAP_NO_CMD_CPL_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58830No Command Completed Support. When set, this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the hot-plug capable Port is able to accept writes to all fields of the Slot Control register without delay between successive writes.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 18180x0RPCIE_CAP_PHY_SLOT_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58849Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis, regardless of the form factor associated with the slot. This field must be initialized to zero for Ports connected to devices that are either integrated on the system board or integrated within the same silicon as the Switch device or Root Port.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31190x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.SLOT_CONTROL_SLOT_STATUSSLOT_CONTROL_SLOT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr591960x18R/W0x000003c0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUSSlot Control and Status Register.This register controls and provides information about PCI Express Slot specific parameters.falsefalsefalsefalsePCIE_CAP_ATTENTION_BUTTON_PRESSED_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58868Attention Button Pressed Enable. When set to 1b, this bit enables software notification on an attention button pressed event (for more details, see Section 6.7.3 of PCI Express Base Specification).If the Attention Button Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b.000x0R/WPCIE_CAP_POWER_FAULT_DETECTED_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58881Power Fault Detected Enable. When set, this bit enables software notification on a power fault event (for more details, see Section 6.7.3 of PCI Express Base Specification).If a Power Controller that supports power fault detection is not implemented, this bit is permitted to be read-only with a value of 0b.110x0R/WPCIE_CAP_MRL_SENSOR_CHANGED_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58894MRL Sensor Changed Enable. When set, this bit enables software notification on a MRL sensor changed event (for more details, see Section 6.7.3 of PCI Express Base Specification).If the MRL Sensor Present bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b.220x0R/WPCIE_CAP_PRESENCE_DETECT_CHANGE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58907Presence Detect Changed Enable. When set, this bit enables software notification on a presence detect changed event (for more details, see Section 6.7.3 of PCI Express Base Specification).If the Hot-Plug Capable bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b.330x0R/WPCIE_CAP_CMD_CPL_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58928Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b), when set, this bit enables software notification when a hot-plug command is completed by the Hot-Plug Controller.If Command Completed notification is not supported, the controller hardwires this bit must to 0b.Write value is gated with PCIE_CAP_NO_CMD_CPL_SUPPORT field in SLOT_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: SLOT_CAPABILITIES_REG.PCIE_CAP_NO_CMD_CPL_SUPPORT ? RO : RW 44R/WPCIE_CAP_HOT_PLUG_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58939Hot-Plug Interrupt Enable. When set, this bit enables generation of an interrupt on enabled hot-plug events.If the Hot Plug Capable bit in the Slot Capabilities register is clear, this bit is permitted to be read-only with a value of 0b.550x0R/WPCIE_CAP_ATTENTION_INDICATOR_CTRLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58962Attention Indicator Control. If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting, if required to, for the previous command to complete in which case the read value is undefined.Defined encodings are: - 00b Reserved - 01b On - 10b Blink - 11b OffNote: The default value of this field must be one of the non-Reserved values. If the Attention Indicator Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 00b.760x3R/WPCIE_CAP_POWER_INDICATOR_CTRLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr58985Power Indicator Control. If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting, if required to, for the previous command to complete in which case the read value is undefined.Defined encodings are: - 00b: Reserved - 01b: On - 10b: Blink - 11b: OffNote: The default value of this field must be one of the non-Reserved values. If the Power Indicator Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 00b.980x3R/WPCIE_CAP_POWER_CONTROLLER_CTRLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59010Power Controller Control. If a Power Controller is implemented, this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write, if required to, without waiting for the previous command to complete in which case the read value is undefined.Note: In some cases the power controller may autonomously remove slot power or not respond to a power-up request based on a detected fault condition, independent of the Power Controller Control setting.The defined encodings are: - 0b: Power On - 1b: Power OffIf the Power Controller Present bit in the Slot Capabilities register is clear, then writes to this bit have no effect and the read value of this bit is undefined.10100x0R/WPCIE_CAP_ELECTROMECH_INTERLOCK_CTRLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59022Electromechanical Interlock Control. If an Electromechanical Interlock is implemented, a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit always returns a 0b.11110x0R/WPCIE_CAP_DLL_STATE_CHANGED_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59036Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b, this bit enables software notification when Data Link Layer Link Active bit is changed.If the Data Link Layer Link Active Reporting Capable bit is 0b, this bit is permitted to be read-only with a value of 0b.12120x0R/W--13130x0rRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59044Reserved for future use.15140x0RPCIE_CAP_ATTENTION_BUTTON_PRESSEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59055Attention Button Pressed. If an Attention Button is implemented, this bit is set when the attention button is pressed. If an Attention Button is not supported, this bit must not be set.16160x0R/W1CPCIE_CAP_POWER_FAULT_DETECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59072Power Fault Detected.If a Power Controller that supports power fault detection is implemented, this bit issSet when the Power Controller detects a power fault at this slot.Note: Depending on hardware capability, it is possible that a power fault can be detected at any time, independent of the Power Controller Control setting or the occupancy of the slot. If power fault detection is not supported, this bit must not be set.17170x0R/W1CPCIE_CAP_MRL_SENSOR_CHANGEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59083MRL Sensor Changed.If an MRL sensor is implemented, this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be set.18180x0R/W1CPCIE_CAP_PRESENCE_DETECTED_CHANGEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59093Presence Detect Changed.This bit is set when the value reported in the Presence Detect State bit is changed.19190x0R/W1CPCIE_CAP_CMD_CPLDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59114Command Completed.If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b), this bit is set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command. The Command Completed status bit is set as an indication to host software that the Hot-Plug Controller has processed the previous command and is ready to receive the next command; it provides no guarantee that the action corresponding to the command is complete.If Command Completed notification is not supported, the controller hardwires this bit to 0b.20200x0R/W1CPCIE_CAP_MRL_SENSOR_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59127MRL Sensor State.This bit reports the status of the MRL sensor if implemented.Defined encodings are: - 0b: MRL Closed - 1b: MRL Open21210x0RPCIE_CAP_PRESENCE_DETECT_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59158Presence Detect State.This bit indicates the presence of an adapter in the slot, reflected by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. Note that the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. Consequently, form factors that require a power controller for hot-plug must implement a physical pin presence detect mechanism.Defined encodings are: -0b: Slot Empty -1b: Adapter Present in slotThis bit must be implemented on all Downstream Ports that implement slots. For Downstream Ports not connected to slots (where the Slot Implemented bit of the PCI Express Capabilities register is 0b), the controller hardwires this bit to 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 2222RPCIE_CAP_ELECTROMECH_INTERLOCK_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59171Electromechanical Interlock Status.If an Electromechanical Interlock is implemented, this bit indicates the status of the Electromechanical Interlock.Defined encodings are: - 0b: Electromechanical Interlock Disengaged - 1b: Electromechanical Interlock Engaged23230x0RPCIE_CAP_DLL_STATE_CHANGEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59187Data Link Layer State Changed.This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed.In response to a Data Link Layer State Changed event, software must read the Data Link Layer Link Active bit of the Link Status register to determine if the Link is active before initiating configuration cycles to the hot plugged device.24240x0R/W1CRSVDP_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59195Reserved for future use.31250x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.ROOT_CONTROL_ROOT_CAPABILITIES_REGROOT_CONTROL_ROOT_CAPABILITIES_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr593080x1CR/W0x00010000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REGRoot Control and Capabilities Register.This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities.falsefalsefalsefalsePCIE_CAP_SYS_ERR_ON_CORR_ERR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59214System Error on Correctable Error Enable. If set, this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific.000x0R/WPCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59226System Error on Non-Fatal Error Enable. If set, this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific.110x0R/WPCIE_CAP_SYS_ERR_ON_FATAL_ERR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59238System Error on Fatal Error Enable. If set, this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port, or by the Root Port itself. The mechanism for signaling a System Error to the system is system specific.220x0R/WPCIE_CAP_PME_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59250PME Interrupt Enable. When set, this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details, see Table 7-29 of PCI Express Base Specification). A PME interrupt is also generated if the PME Status bit is set when this bit is changed from clear to set.330x0R/WPCIE_CAP_CRS_SW_VISIBILITY_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59269CRS Software Visibility Enable. When set, this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details, see section 2.3.1 of PCI Express Base Specification).For Root Ports that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: ROOT_CONTROL_ROOT_CAPABILITIES_REG.PCIE_CAP_CRS_SW_VISIBILITY ? RW : RO 440x0R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59277Reserved for future use.1550x000RPCIE_CAP_CRS_SW_VISIBILITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59299CRS Software Visibility Capable.For a description of this standard PCIe register field, see the PCI Express Base Specification.CRS Software Visibility. When set, this bit indicates that the Root Port is capable of returning Configuration Request Retry Status (CRS) Completion Status to software (for more details, see section 2.3.1 of PCI Express Base Specification).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R (Sticky) Note: This register field is sticky.16160x1RRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59307Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.ROOT_STATUS_REGROOT_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr593570x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_ROOT_STATUS_REGRoot Status Register.The Root Status register provides information about PCI Express device specific parameters.falsefalsefalsefalsePCIE_CAP_PME_REQ_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59323PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set.1500x0000RPCIE_CAP_PME_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59334PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b.16160x0R/W1CPCIE_CAP_PME_PENDINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59348PME Pending. This bit indicates that another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME Requester ID field appropriately. The PME Pending bit is cleared by hardware if no more PMEs are pending.17170x0RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_ROOT_STATUS_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59356Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGDEVICE_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr596190x24R0x80011c1fPE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REGDevice Capabilities 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59396Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value.This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and must be hardwired to 0000b.Four time value ranges are defined: - Range A: 50 us to 10 ms - Range B: 10 ms to 250 ms - Range C: 250 ms to 4 s - Range D: 4 s to 64 sBits are set according to the list below to show timeout value ranges supported. - 0000b Completion Timeout programming not supported – the Function must implement a timeout value in the range 50 μs to 50 ms. - 0001b Range A - 0010b Range B - 0011b Ranges A and B - 0110b Ranges B and C - 0111b Ranges A, B, and C - 1110b Ranges B, C, and D - 1111b Ranges A, B, C, and DAll other values are Reserved.It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.300xfRPCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59414Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism.The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.This mechanism is optional for Root Ports.For all other Functions this field is Reserved and the controller hardwires this bit to 0b.440x1RPCIE_CAP_ARI_FORWARD_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59426ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. For more details, see section 6.13 of PCI Express Base Specification.550x0RPCIE_CAP_ATOMIC_ROUTING_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59438AtomicOp Routing Supported. Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.660x0RPCIE_CAP_32_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5945132-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.770x0RPCIE_CAP_64_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5946464-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.880x0RPCIE_CAP_128_CAS_CPL_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59475128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.990x0RPCIE_CAP_NO_RO_EN_PR2PR_PARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59493No RO-enabled PR-PR Passing. If this bit is set, the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute field being Set.This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit.For all other functions, this bit must be 0b.10100x1RPCIE_CAP_LTR_SUPPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59516LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism.Root Ports, Switches and Endpoints are permitted to implement this capability.For a Multi-Function Device associated with an Upstream Port, each Function must report the same value for this bit.For Bridges and other Functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.11110x1RPCIE_CAP_TPH_CMPLT_SUPPORT_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59535TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions, this field is Reserved.Defined Encodings are: - 00b: TPH and Extended TPH Completer not supported. - 01b: TPH Completer supported; Extended TPH Completer not supported. - 10b: Reserved. - 11b: Both TPH and Extended TPH Completer supported.For more details, see section 6.17 of PCI Express Base Specification.12120x1RPCIE_CAP_TPH_CMPLT_SUPPORT_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59542TPH Completer Supported Bit 1.13130x0RPCIE_CAP2_LN_SYS_CLSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59563LN System CLS. Applicable only to Root Ports and RCRBs; must be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect.Encodings are: - 00b LN Completer either not supported or not in effect - 01b LN Completer with 64-byte cachelines in effect - 10b LN Completer with 128-byte cachelines in effect - 11b ReservedNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 15140x0RPCIE_CAP2_10_BIT_TAG_COMP_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5957310-Bit Tag Completer Supported. If this bit is set, the Function supports 10-Bit Tag Completer capability; otherwise, the Function does not. For more details, see section 2.2.6.2. of PCI Express Base Specification.16160x1RPCIE_CAP2_10_BIT_TAG_REQ_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr5959110-Bit Tag Requester Supported. If this bit is set, the Function supports 10-Bit Tag Requester capability; otherwise, the Function does not.This bit must not be set if the 10-Bit Tag Completer Supported bit is clear.Note: 10-Bit Tag field generation must be enabled by the 10-Bit Tag Requester Enable bit in the Device Control 2 register of the Requester Function before 10-Bit Tags can be generated by the Requester. For more details, see section 2.2.6.2. of PCI Express Base Specification.17170x0R--23180x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59598Reserved for future use.30240x00RPCIE_CAP_FRS_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59618FRS Supported. When set, indicates support for the optional Function Readiness Status (FRS) capability.Must be set for all Functions that support generation or reception capabilities of FRS Messages.Must not be set by Switch Functions that do not generate FRS Messages on their own behalf.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGDEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr597500x28R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REGDevice Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59677Completion Timeout Value. In device Functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and controller hardwires it to 0000b.A Function that does not support this optional capability must hardwire this field to 0000b and is required to implement a timeout value in the range 50 μs to 50 ms. Functions that support Completion Timeout programmability must support the values given below corresponding to the programmability ranges indicated in the Completion Timeout Ranges Supported field.Defined encodings: - 0000b Default range: 50 μs to 50 msIt is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.Values available if Range A (50 μs to 10 ms) programmability range is supported: - 0001b: 50 μs to 100 μs - 0010b: 1 ms to 10 msValues available if Range B (10 ms to 250 ms) programmability range is supported: - 0101b 16 ms to 55 ms - 0110b 65 ms to 210 msValues available if Range C (250 ms to 4 s) programmability range is supported: - 1001b 260 ms to 900 ms - 1010b 1 s to 3.5 sValues available if the Range D (4 s to 64 s) programmability range is supported: - 1101b 4 s to 13 s - 1110b 17 s to 64 sValues not defined above are Reserved.Software is permitted to change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding Requests, and is permitted to base the start time for each Request either on when this value was changed or on when each request was issued.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300x0R/WPCIE_CAP_CPL_TIMEOUT_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59698Completion Timeout Disable. When set, this bit disables the Completion Timeout mechanism.This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this optional capability are permitted to hardwire this bit to 0bSoftware is permitted to set or clear this bit at any time. When set, the Completion Timeout detection mechanism is disabled. If there are outstanding Requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding Requests. If this is done, it is permitted to base the start time for each Request on either the time this bit was cleared or the time each Request was issued.440x0R/WPCIE_CAP_ARI_FORWARD_SUPPORT_CSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59716ARI Forwarding Enable. When set, the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. For more details, see Section 6.13 of PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 550x0R--960x0rPCIE_CAP_LTR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59749LTR Mechanism Enable. When set to 1b, this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages.For a Multi-Function Device associated with an Upstream Port of a device that implements LTR, the bit in Function 0 is RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is RsvdP.Functions that do not implement the LTR mechanism are permitted to hardwire this bit to 0b.For Downstream Ports, this bit must be reset to the default value if the Port goes to DL_Down status.The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.Note: RW for function #0 and RsdvP for all other functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R 1010R/W--31110x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGLINK_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr599160x2CR/W0x81800000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES2_REGLink Capabilities 2 Register.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59761Reserved for future use.000x0RPCIE_CAP_SUPPORT_LINK_SPEED_VECTORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59792Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. For more details, see section 8.2.1 of PCI Express Base Specification.Bit definitions within this field are: - Bit 0 2.5 GT/s - Bit 1 5.0 GT/s - Bit 2 8.0 GT/s - Bit 3 16.0 GT/s - Bit 4 32.0 GT/s - Bits 6:5 RsvdPMulti-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.71RPCIE_CAP_CROSS_LINK_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59821Crosslink Supported. When set to 1b, this bit indicates that the associated Port supports crosslinks (for more details, see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link speeds of 8.0 GT/s or higher, this bit indicates that the associated Port does not support crosslinks. When set to 0b on a Port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, this bit provides no information regarding the Port’s level of crosslink support.It is recommended that this bit be Set in any Port that supports crosslinks even though doing so is only required for Ports that also support operating at 8.0 GT/s or higher Link speeds.Note: Software should use this bit when referencing fields whose definition depends on whether or not the Port supports crosslinks (for more details, see section 7.7.3.4 of PCI Express Base Specification).Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.880x0RRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59829Reserved for future use.2290x0000RPCIE_CAP_RETIMER_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59855Retimer Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 23230x1RPCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59881Two Retimers Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds if the Retimer Presence Detect Supported bit is also set to 1b.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 24240x1R/WRSVDP_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59889Reserved for future use.30250x00RDRS_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59915DRS Supported. When set, indicates support for the optional Device Readiness Status (DRS) capability.Must be Set in Downstream Ports that support DRS.Must be Set in Downstream Ports that support FRS.For Upstream Ports that support DRS, it is strongly recommended that this bit be Set in Function 0. For all other Functions associated with an Upstream Port, this bit must be Clear.127Must be Clear in Functions that are not associated with a Port.RsvdP in all other Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGLINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr604520x30R/W0x00010000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REGLink Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_TARGET_LINK_SPEEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr59980Target Link Speed. For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired target Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.If a value is written to this field that does not correspond to a supported speed (as indicated by the Supported Link Speeds Vector), the result is undefined.If either of the Enter Compliance or Enter Modified Compliance bits are implemented, then this field must also be implemented.The default value of this field is the highest Link speed supported by the component (as reported in the Max Link Speed field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode.For Upstream Ports, if the Enter Compliance bit is Clear, this field is permitted to have no effect.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a description of this standard PCIe register field, see the PCI Express Base Specification. In M-PCIe mode, the contents of this field are derived from other registers.Note: This register field is sticky.30R/WPCIE_CAP_ENTER_COMPLIANCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60013Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link.Default value of this bit following Fundamental Reset is 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: This register field is sticky.440x0R/WPCIE_CAP_HW_AUTO_SPEED_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60038Hardware Autonomous Speed Disable. When set, this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.550x0R/WPCIE_CAP_SEL_DEEMPHASISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60068Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. For more details, see section 4.2.6 of PCI Express Base Specification.Encodings: - 1b: -3.5 dB - 0b: -6 dBWhen the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RPCIE_CAP_TX_MARGINPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60102Transmit Margin – This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base Specification for details of how the Transmitter voltage level is determined in various states).Encodings: - 000b: Normal operating range - 001b-111b: As defined in Section 8.3.4 not all encodings are required to be implemented.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 000b.This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: This register field is sticky.970x0R/WPCIE_CAP_ENTER_MODIFIED_COMPLIANCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60129Enter Modified Compliance. When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.10100x0R/WPCIE_CAP_COMPLIANCE_SOSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60156Compliance SOS. When set to 1b, the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.11110x0R/WPCIE_CAP_COMPLIANCE_PRESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60198Compliance Preset/De-emphasis.For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in section 4.2.3.2 of PCI Express Base Specification . Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way.For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.Defined Encodings are: - 0001b: -3.5 dB - 0000b: -6 dBWhen the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.15120x0R/WPCIE_CAP_CURR_DEEMPHASISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60224Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed, this bit reflects the level of de-emphasis.Encodings: - 1b: -3.5 dB - 0b: -6 dBThe value in this bit is undefined when the Link is not operating at 5.0 GT/s speed.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For components that support speeds greater than 2.5 GT/s, Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions of the Port. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE.16160x1RPCIE_CAP_EQ_CPLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60246Equalization 8.0 GT/s Complete. When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.17170x0RPCIE_CAP_EQ_CPL_P1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60268Equalization 8.0 GT/s Phase 1 Successful. When set to 1b, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.18180x0RPCIE_CAP_EQ_CPL_P2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60290Equalization 8.0 GT/s Phase 2 Successful. When set to 1b, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_EQ_CPL_P3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60312EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.20200x0RPCIE_CAP_LINK_EQ_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60330Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details, see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.21210x0R/W1CPCIE_CAP_RETIMER_PRE_DETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60356Retimer Presence Detected. When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Retimer Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.For Ports that have the Retimer Presence Detect Supported bit set to 0b, the controller hardwires this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and is RsvdZ in all other Functions.Note: This register field is sticky.22220x0RPCIE_CAP_TWO_RETIMERS_PRE_DETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60382Two Retimers Presence Detected. When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and RsvdZ in all other Functions.Note: This register field is sticky.23230x0R--25240x0rRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60390Reserved for future use.27260x0RDOWNSTREAM_COMPO_PRESENCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60430Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component, if any, connected to the Link; defined values are: - 000b: Link Down – Presence Not Determined - 001b: Link Down – Component Not Present indicates the Downstream Port (DP) has determined that a Downstream Component is not present - 010b: Link Down – Component Present indicates the DP has determined that a Downstream Component is present, but the Data Link Layer is not active - 011b: Reserved - 100b: Link Up – Component Presentindicates the DP has determined that a Downstream Component is present, but no DRS Message has been received since the Data Link Layer became active - 101b: Link Up – Component Present and DRS Received indicates the DP has received a DRS Message since the Data Link Layer became active - 110b: Reserved - 111b: ReservedComponent Presence state must be determined by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism implemented for the Link. If no out-of-band presence detect mechanism is implemented, then Component Presence state must be determined solely by the Physical Layer in-band presence detect mechanism.This field must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This field is RsvdZ for all other Functions.30280x0RDRS_MESSAGE_RECEIVEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60451DRS Message Received. This bit must be set whenever the Port receives a DRS Message.This bit must be cleared in DL_Down.This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This bit is RsvdZ for all other Functions.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: RW1C 31310x0R/W1CgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAPPF0_MSIX_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr606550xB0R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAPPF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr605440x0R/W0x00800011PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60472MSI-X Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x11RPCI_MSIX_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60488MSI-X Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x00RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60513MSI-X Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60521Reserved for future use.29270x0RPCI_MSIX_FUNCTION_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60534Function Mask.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30300x0R/WPCI_MSIX_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60543MSI-X Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGMSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr605990x4R0x00000004PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60574MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table BAR Indicator Register" (PCI_MSIX_BIR field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_BIR field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60598MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Offset" (PCI_MSIX_TABLE_OFFSET field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_OFFSET field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGMSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr606540x8R0x00008004PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60629MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA BIR" (PCI_MSIX_PBA_BIR field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_BIR field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60653MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA Offset" (PCI_MSIX_PBA_OFFSET field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_OFFSET field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00001000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAPPF0_AER_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr622550x100R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAPPF Advanced Error Reporting Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFAER_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr607140x0R0x14820001PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_AER_EXT_CAP_HDR_OFFAdvanced Error Reporting Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60681AER Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0001RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60697Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x2RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60713Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x148RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFUNCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr608900x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_UNCORR_ERR_STATUS_OFFUncorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60727Reserved for future use.300x0RDL_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60737Data Link Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.44R/W1CSURPRISE_DOWN_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60747Surprise Down Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.55R/W1CRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60755Reserved for future use.1160x00RPOIS_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60766Poisoned TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CFC_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60776Flow Control Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.1313R/W1CCMPLT_TIMEOUT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60787Completion Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CCMPLT_ABORT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60798Completer Abort Status.For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CUNEXP_CMPLT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60809Unexpected Completion Status.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/W1CREC_OVERFLOW_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60819Receiver Overflow Status.For a description of this standard PCIe register field, see the PCI Express Specification.1717R/W1CMALF_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60829Malformed TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.1818R/W1CECRC_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60843ECRC Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.Note:If CX_ECRC_ENABLE=0 the register field always reads 0.19190x0R/W1CUNSUPPORTED_REQ_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60854Unsupported Request Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.20200x0R/W1C--21210x0rINTERNAL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60873Uncorrectable Internal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.22220x0R/W1CRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60881Reserved for future use.23230x0R--26240x0rRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60889Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFUNCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr610910x8R/W0x00400000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_UNCORR_ERR_MASK_OFFUncorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60903Reserved for future use.300x0RDL_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60914Data Link Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x0R/WSURPRISE_DOWN_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60931Surprise Down Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky.550x0R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60939Reserved for future use.1160x00RPOIS_TLP_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60950Poisoned TLP Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60961Flow Control Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x0R/WCMPLT_TIMEOUT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60972Completion Timeout Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60983Completer Abort Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr60994Unexpected Completion Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61005Receiver Overflow Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x0R/WMALF_TLP_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61016Malformed TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x0R/WECRC_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61030ECRC Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61041Unsupported Request Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/WACS_VIOLATION_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61063ACS Violation Mask.Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors.The bit is Read-Only Zero for upstream ports, when ACS P2P Egress Control Enable is not set.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.21210x0RINTERNAL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61074Uncorrectable Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61082Reserved for future use.23230x0R--26240x0rRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61090Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFUNCORR_ERR_SEV_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr612850xCR/W0x00462030PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_UNCORR_ERR_SEV_OFFUncorrectable Error Severity Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61104Reserved for future use.300x0RDL_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61115Data Link Protocol Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x1R/WSURPRISE_DOWN_ERR_SVRITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61132Surprise Down Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This register field is sticky.550x1R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61140Reserved for future use.1160x00RPOIS_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61151Poisoned TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61162Flow Control Protocol Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCMPLT_TIMEOUT_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61173Completion Timeout Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61184Completer Abort Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61195Unexpected Completion Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61206Receiver Overflow Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x1R/WMALF_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61217Malformed TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x1R/WECRC_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61231ECRC Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61242Unsupported Request Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/W--21210x0rINTERNAL_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61253Uncorrectable Internal Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61261Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_SEVERITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61276AtomicOp Egress Blocked Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61284Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr614030x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_CORR_ERR_STATUS_OFFCorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61301Receiver Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61309Reserved for future use.510x00RBAD_TLP_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61320Bad TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CBAD_DLLP_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61331Bad DLLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.770x0R/W1CREPLAY_NO_ROLEOVER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61342REPLAY_NUM Rollover Status.For a description of this standard PCIe register field, see the PCI Express Specification.880x0R/W1CRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61350Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61361Replay Timer Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CADVISORY_NON_FATAL_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61372Advisory Non-Fatal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.13130x0R/W1CCORRECTED_INT_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61383Corrected Internal Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CHEADER_LOG_OVERFLOW_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61394Header Log Overflow Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61402Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr615210x14R/W0x0000e000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_CORR_ERR_MASK_OFFCorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61419Receiver Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61427Reserved for future use.510x00RBAD_TLP_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61438Bad TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WBAD_DLLP_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61449Bad DLLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x0R/WREPLAY_NO_ROLEOVER_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61460REPLAY_NUM Rollover Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61468Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61479Replay Timer Timeout Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WADVISORY_NON_FATAL_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61490Advisory Non-Fatal Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCORRECTED_INT_ERR_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61501Corrected Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x1R/WHEADER_LOG_OVERFLOW_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61512Header Log Overflow Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x1R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61520Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFADV_ERR_CAP_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr616320x18R/W0x000000a0PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFFAdvanced Error Capabilities and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_ERR_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61540First Error Pointer.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.400x00RECRC_GEN_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61552ECRC Generation Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RECRC_GEN_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61563ECRC Generation Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WECRC_CHECK_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61575ECRC Check Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x1RECRC_CHECK_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61586ECRC Check Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WMULTIPLE_HEADER_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61598Multiple Header Recording Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.990x0RMULTIPLE_HEADER_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61613Multiple Header Recording Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.10100x0R--11110x0rCTO_PRFX_HDR_LOG_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61623TLP Prefix Log Present.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61631Reserved for future use.31130x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFHDR_LOG_0_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr616910x1CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_0_OFFHeader Log Register 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61651Byte 0 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFIRST_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61664Byte 1 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFIRST_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61677Byte 2 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFIRST_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61690Byte 3 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFHDR_LOG_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr617500x20R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_1_OFFHeader Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseSECOND_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61710Byte 0 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RSECOND_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61723Byte 1 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RSECOND_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61736Byte 2 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RSECOND_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61749Byte 3 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFHDR_LOG_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr618090x24R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_2_OFFHeader Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseTHIRD_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61769Byte 0 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RTHIRD_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61782Byte 1 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RTHIRD_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61795Byte 2 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RTHIRD_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61808Byte 3 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFHDR_LOG_3_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr618680x28R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_HDR_LOG_3_OFFHeader Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFOURTH_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61828Byte 0 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFOURTH_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61841Byte 1 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFOURTH_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61854Byte 2 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFOURTH_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61867Byte 3 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ROOT_ERR_CMD_OFFROOT_ERR_CMD_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr619090x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_ROOT_ERR_CMD_OFFRoot Error Command Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCORR_ERR_REPORTING_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61882Correctable Error Reporting Enable.For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/WNON_FATAL_ERR_REPORTING_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61891Non-Fatal Error Reporting Enable.For a description of this standard PCIe register field, see the PCI Express Specification.110x0R/WFATAL_ERR_REPORTING_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61900Fatal Error Reporting Enable.For a description of this standard PCIe register field, see the PCI Express Specification.220x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_CMD_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61908Reserved for future use.3130x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ROOT_ERR_STATUS_OFFROOT_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr620170x30R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_ROOT_ERR_STATUS_OFFRoot Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseERR_COR_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61925Correctable Error Received.For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CMUL_ERR_COR_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61936Multiple Correctable Errors Received.For a description of this standard PCIe register field, see the PCI Express Specification.110x0R/W1CERR_FATAL_NON_FATAL_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61947Fatal or Non-Fatal Error Received.For a description of this standard PCIe register field, see the PCI Express Specification.220x0R/W1CMUL_ERR_FATAL_NON_FATAL_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61958Multiple Fatal or Non-Fatal Errors Received.For a description of this standard PCIe register field, see the PCI Express Specification.330x0R/W1CFIRST_UNCORR_FATALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61969First Uncorrectable Error is Fatal.For a description of this standard PCIe register field, see the PCI Express Specification.440x0R/W1CNON_FATAL_ERR_MSG_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61980One or more Non-Fatal Error Messages Received.For a description of this standard PCIe register field, see the PCI Express Specification.550x0R/W1CFATAL_ERR_MSG_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61991One or more Fatal Error Messages Received.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr61999Reserved for future use.2670x00000RADV_ERR_INT_MSG_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62016Advanced Error Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.ERR_SRC_ID_OFFERR_SRC_ID_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr620500x34R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_ERR_SRC_ID_OFFError Source Identification Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseERR_COR_SOURCE_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62036Source of Correctable Error.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1500x0000RERR_FATAL_NON_FATAL_SOURCE_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62049Source of Fatal/Non-Fatal Error.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFTLP_PREFIX_LOG_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr621010x38R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFFTLP Prefix Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_1_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62067Byte 0 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_1_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62078Byte 1 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_1_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62089Byte 2 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_1_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62100Byte 3 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFTLP_PREFIX_LOG_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr621520x3CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFFTLP Prefix Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_2_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62118Byte 0 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_2_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62129Byte 1 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_2_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62140Byte 2 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_2_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62151Byte 3 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFTLP_PREFIX_LOG_3_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr622030x40R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFFTLP Prefix Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_3_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62169Byte 0 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_3_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62180Byte 1 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_3_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62191Byte 2 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_3_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62202Byte 3 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFTLP_PREFIX_LOG_4_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr622540x44R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFFTLP Prefix Log Register 4.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_4_FIRST_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62220Byte 0 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_4_SECOND_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62231Byte 1 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_4_THIRD_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62242Byte 2 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_4_FOURTH_BYTEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62253Byte 3 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAPPF0_VC_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr632470x148R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAPVirtual Channel Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_BASEregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_BASEVC_BASEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr623140x0R0x19810002PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_BASEVC Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PCIE_EXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62281VC Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0002RVC_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62297Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVC_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62313Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x198RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1VC_CAPABILITIES_REG_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr623840x4R0x00000003PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_1Port VC Capability Register 1.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_EXT_VC_CNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62329Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.200x3RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62336Reserved for future use.330x0RVC_LOW_PRI_EXT_VC_CNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62351Low Priority Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.640x0RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62358Reserved for future use.770x0RVC_REFERENCE_CLOCKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62367Reference Clock.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0RVC_PORT_ARBI_TBL_ENTRY_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62376Port Arbitration Table Entry Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.11100x0RRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62383Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2VC_CAPABILITIES_REG_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr624220x8R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_2Port VC Capability Register 2.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_ARBI_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62405VC Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x1RRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62412Reserved for future use.2340x00000RVC_ARBI_TABLE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62421VC Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGVC_STATUS_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr624730xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_VC_STATUS_CONTROL_REGPort VC Control and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_LOAD_VC_ARBI_TABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62437Requests Hardware to Load VC Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_ARBI_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62446VC Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.310x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62454Reserved for future use.1540x000RVC_ARBI_TABLE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62464VC Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62472Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0RESOURCE_CAP_REG_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr625380x10R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC0VC Resource Capability Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62488Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62495Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62508Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62521Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62528Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62537Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0RESOURCE_CON_REG_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr626270x14R/W0x800000ffPE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC0VC Resource Control Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62553Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RVC_TC_MAP_VC0_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62562Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x7fR/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62570Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62580Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62590Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62598Reserved for future use.23180x00RVC_ID_VCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62608VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62616Reserved for future use.30270x0RVC_ENABLE_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62626VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0RESOURCE_STATUS_REG_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr626670x18R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0VC Resource Status Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62640Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62649Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62659VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62666Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1RESOURCE_CAP_REG_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr627320x1CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC1VC Resource Capability Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62682VC1 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62689Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62702VC1 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62715VC1 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62722Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62731VC1 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1RESOURCE_CON_REG_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr628200x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC1VC Resource Control Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62747VC1 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC1_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62756VC1 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62764Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62774VC1 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62784VC1 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62792Reserved for future use.23200x0RVC_ID_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62802VC1 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62810Reserved for future use.30270x0RVC_ENABLE_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62819VC1 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1RESOURCE_STATUS_REG_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr628600x24R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1VC Resource Status Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62833Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62842VC1 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62852VC1 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62859Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2RESOURCE_CAP_REG_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr629250x28R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC2VC Resource Capability Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62875VC2 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62882Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62895VC2 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62908VC2 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62915Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62924VC2 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2RESOURCE_CON_REG_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr630130x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC2VC Resource Control Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62940VC2 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC2_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62949VC2 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62957Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62967VC2 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62977VC2 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62985Reserved for future use.23200x0RVC_ID_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr62995VC2 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63003Reserved for future use.30270x0RVC_ENABLE_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63012VC2 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2RESOURCE_STATUS_REG_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr630530x30R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2VC Resource Status Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63026Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63035VC2 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63045VC2 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63052Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3RESOURCE_CAP_REG_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr631180x34R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC3VC Resource Capability Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63068VC3 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63075Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63088VC3 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63101VC3 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63108Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63117VC3 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3RESOURCE_CON_REG_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr632060x38R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC3VC Resource Control Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63133VC3 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC3_BIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63142VC3 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63150Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63160VC3 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63170VC3 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63178Reserved for future use.23200x0RVC_ID_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63188VC3 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63196Reserved for future use.30270x0RVC_ENABLE_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63205VC3 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3RESOURCE_STATUS_REG_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr632460x3CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3VC Resource Status Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63219Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63228VC3 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63238VC3 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63245Reserved for future use.31180x0000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAPPF0_SPCIE_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr640870x198R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAPSecondary PCI Express Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGSPCIE_CAP_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr633060x0R0x1b810019PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REGSPCIE Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63273Secondary PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0019RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63289Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63305Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1b8RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGLINK_CONTROL3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr633460x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_LINK_CONTROL3_REGLink Control 3 Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalsePERFORM_EQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63324Perform Equalization.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 00R/WEQ_REQ_INT_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63337Link Equalization Request Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63345Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGLANE_ERR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr633710x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_LANE_ERR_STATUS_REGLane Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseLANE_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63362Lane Error Status Bits per Lane.For a description of this standard PCIe register field, see the PCI Express Specification.700x00R/W1CRSVDP_LANE_ERR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63370Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGSPCIE_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr635460xCR0x7f7f7f7fPE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REGLane Equalization Control Register for lanes 1 and 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63392Downstream Port 8.0 GT/s Transmitter Preset 0.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63407Downstream Port 8.0 GT/s Receiver Preset Hint 0.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63414Reserved for future use.770x0RUSP_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63434Upstream Port 8.0 GT/s Transmitter Preset 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63454Upstream Port 8.0 GT/s Receiver Preset Hint 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63461Reserved for future use.15150x0RDSP_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63476Downstream Port 8.0 GT/s Transmitter Preset 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63491Downstream Port 8.0 GT/s Receiver Preset Hint 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63498Reserved for future use.23230x0RUSP_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63518Upstream Port 8.0 GT/s Transmitter Preset 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63538Upstream Port 8.0 GT/s Receiver Preset Hint 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63545Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGSPCIE_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr637260x10R0x7f7f7f7fPE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63572Downstream Port 8.0 GT/s Transmitter Preset2.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63587Downstream Port 8.0 GT/s Receiver Preset Hint2.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63594Reserved for future use.770x0RUSP_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63614Upstream Port 8.0 GT/s Transmitter Preset2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63634Upstream Port 8.0 GT/s Receiver Preset Hint2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63641Reserved for future use.15150x0RDSP_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63656Downstream Port 8.0 GT/s Transmitter Preset3.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63671Downstream Port 8.0 GT/s Receiver Preset Hint3.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63678Reserved for future use.23230x0RUSP_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63698Upstream Port 8.0 GT/s Transmitter Preset3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63718Upstream Port 8.0 GT/s Receiver Preset Hint3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63725Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGSPCIE_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr639060x14R0x7f7f7f7fPE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63752Downstream Port 8.0 GT/s Transmitter Preset4.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63767Downstream Port 8.0 GT/s Receiver Preset Hint4.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63774Reserved for future use.770x0RUSP_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63794Upstream Port 8.0 GT/s Transmitter Preset4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63814Upstream Port 8.0 GT/s Receiver Preset Hint4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63821Reserved for future use.15150x0RDSP_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63836Downstream Port 8.0 GT/s Transmitter Preset5.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63851Downstream Port 8.0 GT/s Receiver Preset Hint5.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63858Reserved for future use.23230x0RUSP_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63878Upstream Port 8.0 GT/s Transmitter Preset5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63898Upstream Port 8.0 GT/s Receiver Preset Hint5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63905Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGSPCIE_CAP_OFF_18H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr640860x18R0x7f7f7f7fPE0_DWC_pcie_ctl_DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63932Downstream Port 8.0 GT/s Transmitter Preset6.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 300xfRDSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63947Downstream Port 8.0 GT/s Receiver Preset Hint6.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 640x7RRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63954Reserved for future use.770x0RUSP_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63974Upstream Port 8.0 GT/s Transmitter Preset6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 1180xfRUSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr63994Upstream Port 8.0 GT/s Receiver Preset Hint6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 14120x7RRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64001Reserved for future use.15150x0RDSP_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64016Downstream Port 8.0 GT/s Transmitter Preset7.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 19160xfRDSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64031Downstream Port 8.0 GT/s Receiver Preset Hint7.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 22200x7RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64038Reserved for future use.23230x0RUSP_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64058Upstream Port 8.0 GT/s Transmitter Preset7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 27240xfRUSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64078Upstream Port 8.0 GT/s Receiver Preset Hint7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R(sticky)) : ROS 30280x7RRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64085Reserved for future use.31310x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAPPF0_PL16G_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr645700x1B8R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAPPhysical Layer 16.0 GT/s Extended Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPL16G_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr641460x0R0x1e010026PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REGPhysical Layer 16.0 GT/s Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64113PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0026RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64129Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64145Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1e0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPL16G_CAPABILITY_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr641600x4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CAPABILITY_REG16.0 GT/s Capabilities Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64159Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPL16G_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr641740x8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CONTROL_REG16.0 GT/s Control Register .For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64173Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPL16G_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr642550xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_STATUS_REG16.0 GT/s Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEQ_16G_CPLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64193Equalization 16.0GT/s Complete.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.000x0REQ_16G_CPL_P1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64207Equalization 16.0GT/s Phase 1 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.110x0REQ_16G_CPL_P2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64221Equalization 16.0GT/s Phase 2 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.220x0REQ_16G_CPL_P3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64235Equalization 16.0GT/s Phase 3 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.330x0RLINK_EQ_16G_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64246Link Equalization Request 16.0GT/s.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.440x0R/W1CRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64254Reserved for future use.3150x0000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPL16G_LC_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr642800x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG16.0 GT/s Local Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseLC_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64271Local Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_LC_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64279Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr643050x14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG16.0 GT/s First Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseFIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64296First Retimer Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_FIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64304Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr643310x18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG16.0 GT/s Second Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseSECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64322Second Retimer Data Parity Mismatch Status .For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_SECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64330Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPL16G_CAP_OFF_20H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr644500x20R0xffffffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG16.0 GT/s Lane Equalization Control Register for Lane 0-3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64351Downstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 300xfRUSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64365Upstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 740xfRDSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64379Downstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 1180xfRUSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64393Upstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 15120xfRDSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64407Downstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 19160xfRUSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64421Upstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 23200xfRDSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64435Downstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 27240xfRUSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64449Upstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31280xfRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPL16G_CAP_OFF_24H_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr645690x24R0xffffffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG16.0 GT/s Lane Equalization Control Register for Lane 4-7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64470Downstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 300xfRUSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64484Upstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 740xfRDSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64498Downstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 1180xfRUSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64512Upstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 15120xfRDSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64526Downstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 19160xfRUSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64540Upstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 23200xfRDSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64554Downstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 27240xfRUSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64568Upstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31280xfRgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAPPF0_MARGIN_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr655590x1E0R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAPMargining Extended Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGMARGIN_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr646290x0R0x20810027PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REGMargining Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64596PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0027RCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64612Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64628Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x208RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGMARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr646860x4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REGMargining Port Capabilities and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseMARGINING_USES_DRIVER_SOFTWAREPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64651Margining uses Driver Software.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64658Reserved for future use.1510x0000RMARGINING_READYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64668Margining Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1616RMARGINING_SOFTWARE_READYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64678Margining Software Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1717RRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64685Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGMARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr647950x8R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REGMargining Lane Control and Status Register for Lane 0.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64700Receiver Number for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64710Margin Type for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64720Usage Model for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64728Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64738Margin Payload for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64750Receiver Number(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64762Margin Type(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64774Usage Model(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64782Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64794Margin Payload(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGMARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr649040xCR/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REGMargining Lane Control and Status Register for Lane 1.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64809Receiver Number for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64819Margin Type for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64829Usage Model for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64837Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64847Margin Payload for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64859Receiver Number(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64871Margin Type(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64883Usage Model(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64891Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64903Margin Payload(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGMARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr650130x10R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REGMargining Lane Control and Status Register for Lane 2.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64918Receiver Number for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64928Margin Type for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64938Usage Model for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64946Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64956Margin Payload for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64968Receiver Number(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64980Margin Type(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr64992Usage Model(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65000Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65012Margin Payload(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGMARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr651220x14R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REGMargining Lane Control and Status Register for Lane 3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65027Receiver Number for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65037Margin Type for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65047Usage Model for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65055Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65065Margin Payload for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65077Receiver Number(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65089Margin Type(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65101Usage Model(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65109Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65121Margin Payload(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGMARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr652310x18R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REGMargining Lane Control and Status Register for Lane 4.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65136Receiver Number for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65146Margin Type for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65156Usage Model for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65164Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65174Margin Payload for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65186Receiver Number(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65198Margin Type(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65210Usage Model(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65218Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65230Margin Payload(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGMARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr653400x1CR/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REGMargining Lane Control and Status Register for Lane 5.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65245Receiver Number for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65255Margin Type for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65265Usage Model for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65273Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65283Margin Payload for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65295Receiver Number(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65307Margin Type(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65319Usage Model(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65327Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65339Margin Payload(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGMARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr654490x20R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REGMargining Lane Control and Status Register for Lane 6.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65354Receiver Number for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65364Margin Type for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65374Usage Model for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65382Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65392Margin Payload for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65404Receiver Number(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65416Margin Type(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65428Usage Model(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65436Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65448Margin Payload(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGMARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr655580x24R/W0x00009c38PE0_DWC_pcie_ctl_DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REGMargining Lane Control and Status Register for Lane 7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65463Receiver Number for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65473Margin Type for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65483Usage Model for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65491Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65501Margin Payload for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65513Receiver Number(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65525Margin Type(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65537Usage Model(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65545Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65557Margin Payload(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAPPF0_TPH_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr658400x208R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAPPF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGTPH_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr656180x0R0x29c10017PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REGTPH Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCIE_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65585TPH Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0017RTPH_REQ_CAP_VERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65601Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RTPH_REQ_NEXT_PTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65617Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x29cRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGTPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr657570x4R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_REQ_CAP_REG_REGTPH Requestor Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65640No ST Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65656Interrupt Vector Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65672Device Specific Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65679Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65695Extended TPH Requester Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65711ST Table Location Bit 0.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65727ST Table Location Bit 1.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65734Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65749ST Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65756Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGTPH_REQ_CONTROL_REG_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr658020x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REGTPH Requestor Control Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_MODE_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65776ST Mode Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65784Reserved for future use.730x00RTPH_REQ_CTRL_REQ_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65793TPH Requester Enable Bit.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65801Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0TPH_ST_TABLE_REG_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr658390xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_TPH_ST_TABLE_REG_0TPH ST Table Register 0.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_TABLE_LOWER_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65822ST Table 0 Lower Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: this field is RW or Tie to 0 by table size configure 700x00R/WTPH_REQ_ST_TABLE_HIGHER_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65838ST Table 0 Upper Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: this field is RW or Tie to 0 by table size configure 1580x00R--31160x0rgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAPPF0_L1SUB_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr662800x29CR/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAPL1 Substates Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGL1SUB_CAP_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr65914L1 Substates Extended Capability Header provides capbility ID, capability version and next offset value for L1 Substates.0x0R0x2ac1001ePE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REGL1 Substates Extended Capability Header.This register provides capbility ID, capability version and next offset value for L1 Substates.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65871L1SUB Extended Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for L1 PM Substates is 001Eh.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001eRCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65888Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65913Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2acRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGL1SUB_CAPABILITY_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr66079This register provides extended capability of L1 Substates.0x4R/W0x00380a1fPE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REGL1 Substates Capability Register.This register provides extended capability of L1 Substates.falsefalsefalsefalseL1_2_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65932PCI-PM L12 Supported.When Set this bit indicates that PCI-PM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 000x1R/WL1_1_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65945PCI-PM L11 Supported.When Set this bit indicates that PCI-PM L1.1 is supported, and must be Set by all Ports implementing L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 110x1R/WL1_2_ASPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65957ASPM L12 Supported.When Set this bit indicates that ASPM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 220x1R/WL1_1_ASPM_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65969ASPM L11 Supported.When Set this bit indicates that ASPM L1.1 is supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 330x1R/WL1_PMSUB_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65982L1 PM Substates ECN Supported.When Set this bit indicates that this Port supports L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) 440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr65990Reserved for future use.750x0RCOMM_MODE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66009Port Common Mode Restore Time.Time (in us) required for this Port to re-establish common mode.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 1580x0aR/WPWR_ON_SCALE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66036Port T Power On Scale.Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register.Range of values are given below.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 17160x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66044Reserved for future use.18180x0RPWR_ON_VALUE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66070Port T Power On Value.Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. Default value is 00101b.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 23190x07R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66078Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGL1SUB_CONTROL1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr66199This register provides Controls to extended capability.0x8R/W0x00000a00PE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL1_REGL1 Substates Control 1 Register.This register provides Controls to extended capability.falsefalsefalsefalseL1_2_PCIPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66095PCI-PM L12 Enable.When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.000x0R/WL1_1_PCIPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66104PCI-PM L11 Enable.When Set this bit enables PCI-PM L1.1. Default value is 0b.110x0R/WL1_2_ASPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66114ASPM L12 Enable.When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.220x0R/WL1_1_ASPM_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66124ASPM L11 Enable.When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66132Reserved for future use.740x0RT_COMMON_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66151Common Mode Restore Time.Sets value of TCOMMONMODE (in μs), which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports.Default value is implementation specific.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RW : RSVDP 1580x0aR/WL1_2_TH_VALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66170LTR L12 Threshold Value.Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b.Required for all Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 25160x000R/WRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66178Reserved for future use.28260x0RL1_2_TH_SCAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66198LTR L12 Threshold Scale.This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field.Required for all Ports Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 31290x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGL1SUB_CONTROL2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr66279This register provides Controls to extended capability.0xCR/W0x00000028PE0_DWC_pcie_ctl_DBI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL2_REGL1 Substates Control 2 Register.This register provides Controls to extended capability.falsefalsefalsefalseT_POWER_ON_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66235T Power On Scale.Specifies the scale used for T_POWER_ON Value.Range of values are given below.Required for all Ports that support L1.2, otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 100x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66243Reserved for future use.220x0RT_POWER_ON_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66270T Power On Value.Along with the T_POWER_ON Scale sets the minimum amount of time (in μs) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b.T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.Required for all Ports that support L1.2, otherwise this field is of type RsvdP.This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 730x05R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66278Reserved for future use.3180x000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAPPF0_FRSQ_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr664690x2ACR/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_FRSQ_CAPPF FRSQ Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_EXT_CAP_HDR_OFFFRSQ_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr663390x0R0x2c410021PE0_DWC_pcie_ctl_DBI_Slave_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFFFRS Queuing Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRSQ_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66306PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0021RFRSQ_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66322Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RFRSQ_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_EXT_CAP_HDR_OFF_FRSQ_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66338Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2c4RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_CAP_OFFFRSQ_CAP_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr663840x4R0x00000008PE0_DWC_pcie_ctl_DBI_Slave_PF0_FRSQ_CAP_FRSQ_CAP_OFFFRS Queuing Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRSQ_MAX_DEPTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRSQ_MAX_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66354FRS Queue Max Depth.For a description of this standard PCIe register field, see the PCI Express Specification.1100x008RRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66361Reserved for future use.15120x0RFRS_INT_MESSAGE_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_FRS_INT_MESSAGE_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66376FRS Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CAP_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66383Reserved for future use.31210x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRSQ_CONTROL_FRSQ_STATUS_OFFFRSQ_CONTROL_FRSQ_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr664370x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFFFRS Queuing Status and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRS_MESSAGE_RECEIVEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_RECEIVED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66400FRS Message Received.For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CFRS_MESSAGE_OVERFLOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_MESSAGE_OVERFLOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66411FRS Message Overflow.For a description of this standard PCIe register field, see the PCI Express Specification.110x0R/W1CRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66419Reserved for future use.1520x0000RFRS_INTERRUPT_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_FRS_INTERRUPT_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66428FRS Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRSQ_CONTROL_FRSQ_STATUS_OFF_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66436Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_FRSQ_CAP.FRS_MESSAGE_QUEUE_OFFFRS_MESSAGE_QUEUE_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr664680xCRPE0_DWC_pcie_ctl_DBI_Slave_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFFFRS Message Queue Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFRS_MESSAGE_QUE_FUNC_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_FUNC_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66451FRS Message Queue Function ID.For a description of this standard PCIe register field, see the PCI Express Specification.150RFRS_MESSAGE_QUE_REASONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_REASON_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66459FRS Message Queue Reason.For a description of this standard PCIe register field, see the PCI Express Specification.1916RFRS_MESSAGE_QUE_DEPTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_FRSQ_CAP_FRS_MESSAGE_QUEUE_OFF_FRS_MESSAGE_QUE_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66467FRS Message Queue Depth.For a description of this standard PCIe register field, see the PCI Express Specification.3120RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAPPF0_RAS_DES_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr697090x2C4R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAPRAS D.E.S. Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGRAS_DES_CAP_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr665280x0R0x3c41000bPE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REGVendor-Specific Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66495PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66511Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66527Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3c4RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGVENDOR_SPECIFIC_HEADER_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr665620x4R0x10040002PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REGVendor-Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66543VSEC ID.For a description of this standard PCIe register field, see the PCI Express Specification.1500x0002RVSEC_REVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66552VSEC Rev.For a description of this standard PCIe register field, see the PCI Express Specification.19160x4RVSEC_LENGTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66561VSEC Length.For a description of this standard PCIe register field, see the PCI Express Specification.31200x100RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGEVENT_COUNTER_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr667090x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REGEvent Counter Control.This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.falsefalsefalsefalseEVENT_COUNTER_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66603Event Counter Clear.Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code.The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved100x0WEVENT_COUNTER_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66629Event Counter Enable.Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.By default, all event counters are disabled.You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes.You can enable/disable all event counters by writing the 'all on' or 'all off' codes.The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on420x0WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66637Reserved for future use.650x0REVENT_COUNTER_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66652Event Counter Status.This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECTNote: This register field is sticky.770x0REVENT_COUNTER_LANE_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66669Event Counter Lane Select.This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66677Reserved for future use.15120x0REVENT_COUNTER_EVENT_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66700Event Counter Data Select.This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the GroupFor example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLPFor detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.Note: This register field is sticky.27160x000R/WRSVDP_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66708Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGEVENT_COUNTER_DATA_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr667340xCR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REGEvent Counter Data.This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEVENT_COUNTER_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66733Event Counter Data.This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGNote: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGTIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr668500x10R/W0x00000100PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REGTime-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIMER_STARTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66758Timer Start. - 1: Start/Restart - 0: StopThis bit will be cleared automatically when the measurement is finished.Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66766Reserved for future use.710x00RTIME_BASED_DURATION_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66788Time-based Duration Select.Selects the duration of time-based analysis.When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - 0xff: 4us (Debug purpose) - Else: ReservedNote: This register field is sticky.1580x01R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66796Reserved for future use.23160x00RTIME_BASED_REPORT_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66849Time-based Report Select.Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA.Each type of data is measured using one of three types of units: - Core_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Core_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate). Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x10] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATACore_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 - 0x07: Configuration/Recovery - 0x08: TxL0s and RxL0sAux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 - 0x09: L1 auxCore_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate) - 0x10: Duration of 1 cycle - 0x11: TxL0s - 0x12: RxL0s - 0x13: L0 - 0x14: L1 - 0x17: Configuration/Recovery - 0x18: TxL0s and RxL0sData Bytes - 0x20: Tx PCIe TLP data payload Bytes - 0x21: Rx PCIe TLP data payload Bytes - 0x22: Tx CCIX TLP data payload Bytes - 0x23: Rx CCIX TLP data payload Bytes - Else: RsvdNote: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGTIME_BASED_ANALYSIS_DATA_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr668770x14R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REGTime-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66876Time Based Analysis Data.This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.The results are cleared when next measurement starts.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGTIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr668980x18R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REGUpper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATA_63_32PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66897Upper 32 bits of Time Based Analysis Data.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGEINJ_ENABLE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr670350x30R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ_ENABLE_REGError Injection Enable.Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REGAfter the errors have been inserted by controller, it will clear each bit here.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_INJECTION0_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66931Error Injection0 Enable (CRC Error).Enables insertion of errors into various CRC.For more details, see the EINJ0_CRC_REG register.Note: This register field is sticky.000x0R/WERROR_INJECTION1_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66945Error Injection1 Enable (Sequence Number Error).Enables insertion of errors into sequence numbers.For more details, see the EINJ1_SEQNUM_REG register.Note: This register field is sticky.110x0R/WERROR_INJECTION2_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66959Error Injection2 Enable (DLLP Error).Enables insertion of DLLP errors.For more details, see the EINJ2_DLLP_REG register.Note: This register field is sticky.220x0R/WERROR_INJECTION3_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66975Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).Enables DataK masking of special symbols or the breaking of the sync header.For more details, see the EINJ3_SYMBOL_REG register.Note: This register field is sticky.330x0R/WERROR_INJECTION4_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr66989Error Injection4 Enable (FC Credit Update Error).Enables insertion of errors into UpdateFCs.For more details, see the EINJ4_FC_REG register.Note: This register field is sticky.440x0R/WERROR_INJECTION5_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67003Error Injection5 Enable (TLP Duplicate/Nullify Error).Enables insertion of duplicate/nullified TLPs.For more details, see the EINJ5_SP_TLP_REG register.Note: This register field is sticky.550x0R/WERROR_INJECTION6_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67026Error Injection6 Enable (Specific TLP Error).Enables insertion of errors into the packets that you select.You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0.For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.Note: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67034Reserved for future use.3170x0000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGEINJ0_CRC_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr671050x34R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ0_CRC_REGError Injection Control 0 (CRC Error).Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side.falsefalsefalsefalseEINJ0_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67073Error injection count.Indicates the number of errors.This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ0_CRC_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67096Error injection type.Selects the type of CRC error to be inserted.Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b)Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: ReservedNote: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67104Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGEINJ1_SEQNUM_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr672030x38R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REGError Injection Control 1 (Sequence Number Error).Controls the sequence number of the specific TLPs and ACK/NAK DLLPs.Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048falsefalsefalsefalseEINJ1_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67140Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ1_SEQNUM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67152Sequence number type.Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# ErrorNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67160Reserved for future use.1590x00REINJ1_BAD_SEQNUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67194Bad sequence number.Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link.Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67202Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGEINJ2_DLLP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr672630x3CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ2_DLLP_REGError Injection Control 2 (DLLP Error).Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.falsefalsefalsefalseEINJ2_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67240Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'.This register is affected only when EINJ2_DLLP_TYPE =2'10b.Note: This register field is sticky.700x00R/WEINJ2_DLLP_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67254DLLP Type.Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: ReservedNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67262Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGEINJ3_SYMBOL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr673230x40R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REGError Injection Control 3 (Symbol Error).When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.When 128b/130b encoding is used, this register controls error insertion into the sync-header.falsefalsefalsefalseEINJ3_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67291Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ3_SYMBOL_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67314Error Type.8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set)128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67322Reserved for future use.31110x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGEINJ4_FC_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr674280x44R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ4_FC_REGError Injection Control 4 (FC Credit Error).Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data creditThese errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.falsefalsefalsefalseEINJ4_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67354Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ4_UPDFC_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67372Update-FC type.Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67380Reserved for future use.11110x0REINJ4_VC_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67391VC Number.Indicates target VC Number.Note: This register field is sticky.14120x0R/WRSVDP_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67399Reserved for future use.15150x0REINJ4_BAD_UPDFC_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67419Bad update-FC credit value.Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67427Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGEINJ5_SP_TLP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr674850x48R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REGError Injection Control 5 (Specific TLP Error).Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.falsefalsefalsefalseEINJ5_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67462Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ5_SPECIFIED_TLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67476Specified TLP.Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer).Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67484Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGEINJ6_COMPARE_POINT_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr675230x4CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REGError Injection Control 6 (Compare Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67522Packet Compare Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGEINJ6_COMPARE_POINT_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr675610x50R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REGError Injection Control 6 (Compare Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67560Packet Compare Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGEINJ6_COMPARE_POINT_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr675970x54R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REGError Injection Control 6 (Compare Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67596Packet Compare Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGEINJ6_COMPARE_POINT_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr676350x58R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REGError Injection Control 6 (Compare Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67634Packet Compare Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGEINJ6_COMPARE_VALUE_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr676690x5CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REGError Injection Control 6 (Compare Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67668Packet Compare Value: 1st DWORD.Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGEINJ6_COMPARE_VALUE_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr677030x60R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REGError Injection Control 6 (Compare Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67702Packet Compare Value: 2nd DWORD.Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGEINJ6_COMPARE_VALUE_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr677370x64R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REGError Injection Control 6 (Compare Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67736Packet Compare Value: 3rd DWORD.Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGEINJ6_COMPARE_VALUE_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr677710x68R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REGError Injection Control 6 (Compare Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67770Packet Compare Value: 4th DWORD.Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGEINJ6_CHANGE_POINT_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr678030x6CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REGError Injection Control 6 (Change Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67802Packet Change Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGEINJ6_CHANGE_POINT_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr678350x70R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REGError Injection Control 6 (Change Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67834Packet Change Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGEINJ6_CHANGE_POINT_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr678670x74R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REGError Injection Control 6 (Change Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67866Packet Change Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGEINJ6_CHANGE_POINT_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr678990x78R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REGError Injection Control 6 (Change Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67898Packet Change Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGEINJ6_CHANGE_VALUE_H0_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr679340x7CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REGError Injection Control 6 (Change Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67933Packet Change Value: 1st DWORD.Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGEINJ6_CHANGE_VALUE_H1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr679690x80R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REGError Injection Control 6 (Change Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr67968Packet Change Value: 2nd DWORD.Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGEINJ6_CHANGE_VALUE_H2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr680040x84R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REGError Injection Control 6 (Change Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68003Packet Change Value: 3rd DWORD.Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGEINJ6_CHANGE_VALUE_H3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr680390x88R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REGError Injection Control 6 (Change Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68038Packet Change Value: 4th DWORD.Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGEINJ6_TLP_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr681200x8CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_EINJ6_TLP_REGError Injection Control 6 (Packet Error).The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the this register.The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register.Only applies when EINJ6_INVERTED_CONTROL in this register =0.The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bitfalsefalsefalsefalseEINJ6_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68083Error Injection Count.Indicates the number of errors to insert.This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ6_INVERTED_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68096Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].Note: This register field is sticky.880x0R/WEINJ6_PACKET_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68111Packet type.Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: ReservedNote: This register field is sticky.1190x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68119Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGSD_CONTROL1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr682170xA0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_CONTROL1_REGSilicon Debug Control 1.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_DETECT_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68143Force Detect Lane.When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15Note: This register field is sticky.1500x0000R/WFORCE_DETECT_LANE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68157Force Detect Lane Enable.When this bit is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68165Reserved for future use.19170x0RTX_EIOS_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68190Number of Tx EIOS.This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification.2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 165.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32Note: This register field is sticky.21200x0R/WLOW_POWER_INTERVALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68208Low Power Entry Interval Time.Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640nsNote: This register field is sticky.23220x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68216Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGSD_CONTROL2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr683400xA4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_CONTROL2_REGSilicon Debug Control 2.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseHOLD_LTSSMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68235Hold and Release LTSSM.For as long as this register is '1', the controller stays in the current LTSSM.Note: This register field is sticky.000x0R/WRECOVERY_REQUESTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68248Recovery Request.When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.110x0WNOACK_FORCE_LINKDOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68262Force LinkDown.When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.Note: This register field is sticky.220x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68270Reserved for future use.730x00RDIRECT_RECIDLE_TO_CONFIGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68283Direct Recovery.Idle to Configuration.When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.Note: This register field is sticky.880x0R/WDIRECT_POLCOMP_TO_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68296Direct Polling.Compliance to Detect.When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.Note: This register field is sticky.990x0R/WDIRECT_LPBKSLV_TO_EXITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68310Direct Loopback Slave To Exit.When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.Note: This register field is sticky.10100x0R/WRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68318Reserved for future use.15110x00RFRAMING_ERR_RECOVERY_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68331Framing Error Recovery Disable.This bit disables a transition to Recovery state when a Framing Error is occurred.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68339Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGSD_STATUS_L1LANE_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr684720xB0R/W0x00180000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REGSilicon Debug Status(Layer1 Per-lane).This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseLANE_SELECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68365Lane Select.Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68373Reserved for future use.1540x000RPIPE_RXPOLARITYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68388PIPE:RxPolarity.Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).Note: This register field is sticky.16160x0RPIPE_DETECT_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68403PIPE:Detect Lane.Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).Note: This register field is sticky.17170x0RPIPE_RXVALIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68418PIPE:RxValid.Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).Note: This register field is sticky.18180x0RPIPE_RXELECIDLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68433PIPE:RxElecIdle.Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.19190x1RPIPE_TXELECIDLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68448PIPE:TxElecIdle.Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.20200x1RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68456Reserved for future use.23210x0RDESKEW_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68471Deskew Pointer.Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGSD_STATUS_L1LTSSM_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr686210xB4R/W0x00000200PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REGSilicon Debug Status(Layer1 LTSSM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFRAMING_ERR_PTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68541First Framing Error Pointer.Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1.Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit controller only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder.Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS stateAll other values not listed above are Reserved.Note: This register field is sticky.600x00RFRAMING_ERRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68552Framing Error.Indicates Framing Error detection status.770x0R/W1CPIPE_POWER_DOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68566PIPE:PowerDown.Indicates PIPE PowerDown signal.Note: This register field is sticky.1080x2RRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68574Reserved for future use.14110x0RLANE_REVERSALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68590Lane Reversal Operation.Receiver detected lane reversal.This field is only valid in the L0 LTSSM state.Note: This register field is sticky.15150x0RLTSSM_VARIABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68620LTSSM Variable.Indicates internal LTSSM variables defined in the PCI Express Base Specification.C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitionedM-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configurationNote: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGSD_STATUS_PM_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr687620xB8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_PM_REGSilicon Debug Status(PM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseINTERNAL_PM_MSTATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68663Internal PM State(Master).Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP - 19h: WAIT_DSTATE_UPDATENote: This register field is sticky.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68671Reserved for future use.750x0RINTERNAL_PM_SSTATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68698Internal PM State(Slave).Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch: S_WAIT_LAST_PMDLLPNote: This register field is sticky.1180x0RPME_RESEND_FLAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68712PME Re-send flag.When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.12120x0R/W1CL1SUB_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68738L1Sub State.Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check clkreq_in_n is de-asserted for t_power_off time (only for L1.2, reduces to one cycle for L1.1) - 5h: S_L1_N : L1 substate, turn off txcommonmode circuits (L1.2 only) and rx electrical idle detection circuits - 6h: S_L1_N_EXIT : locally/remotely initiated exit, assert pclkreq, wait for pclkack - 7h: S_L1_N_ABORT : wait for pclkack when aborting an attempt to enter L1_NNote: This register field is sticky.15130x0RLATCHED_NFTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68753Latched N_FTS.Indicates the value of N_FTS in the received TS Ordered Sets from the Link PartnerNote: This register field is sticky.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68761Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGSD_STATUS_L2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr688430xBCR0x00fff000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L2_REGSilicon Debug Status(Layer2).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTX_TLP_SEQ_NOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68781Tx Tlp Sequence Number.Indicates next transmit sequence number for transmit TLP.Note: This register field is sticky.1100x000RRX_ACK_SEQ_NOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68795Tx Ack Sequence Number.Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.Note: This register field is sticky.23120xfffRDLCMSMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68810DLCMSM.Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVENote: This register field is sticky.25240x0RFC_INIT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68823FC_INIT1.Indicates the controller is in FC_INIT1(VC0) state.Note: This register field is sticky.26260x0RFC_INIT2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68835FC_INIT2.Indicates the controller is in FC_INIT2(VC0) state.Note: This register field is sticky.27270x0RRSVDP_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68842Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGSD_STATUS_L3FC_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr689670xC0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REGSilicon Debug Status(Layer3 FC).The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HDFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseCREDIT_SEL_VCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68874Credit Select(VC).This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7Note: This register field is sticky.200x0R/WCREDIT_SEL_CREDIT_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68890Credit Select(Credit Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: TxNote: This register field is sticky.330x0R/WCREDIT_SEL_TLP_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68907Credit Select(TLP Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: CompletionNote: This register field is sticky.540x0R/WCREDIT_SEL_HDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68923Credit Select(HeaderData).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data CreditNote: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68931Reserved for future use.770x0RCREDIT_DATA0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68948Credit Data0.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed ValueNote: This register field is sticky.1980x000RCREDIT_DATA1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr68966Credit Data1.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE).Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGSD_STATUS_L3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr690230xC4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3_REGSilicon Debug Status(Layer3).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseMFTLP_POINTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69003First Malformed TLP Error Pointer.Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: ReservedNote: This register field is sticky.600x00RMFTLP_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69014Malformed TLP Status.Indicates malformed TLP has occurred.770x0R/W1CRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69022Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGSD_EQ_CONTROL1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr691630xD0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REGSilicon Debug EQ Control 1.This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LANE_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69051EQ Status Lane Select.Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WEQ_RATE_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69068EQ Status Rate Select.Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed (include ESM data rate) - 0x1: 16.0GT/s Speed (include ESM data rate) - 0x2: 32.0GT/s SpeedNote: This register field is sticky.540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69076Reserved for future use.760x0REXT_EQ_TIMEOUTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69100Extends EQ Phase2/3 Timeout.This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set, the value of EQ2/3 timeout is extended.EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeoutEQ Slave(DSP in EQ Phase2/USP in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No timeoutNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69108Reserved for future use.15100x00REVAL_INTERVAL_TIMEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69126Eval Interval Time.Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4usThis field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).Note: This register field is sticky.17160x0R/WRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69134Reserved for future use.22180x00RFOM_TARGET_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69146FOM Target Enable.Enables the FOM_TARGET fields.Note: This register field is sticky.23230x0R/WFOM_TARGETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69162FOM Target.Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).Note: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGSD_EQ_CONTROL2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr693070xD4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REGSilicon Debug EQ Control 2.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_LOCAL_TX_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69185Force Local Transmitter Pre-cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.500x00R/WFORCE_LOCAL_TX_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69199Force Local Transmitter Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.1160x00R/WFORCE_LOCAL_TX_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69213Force Local Transmitter Post-Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.17120x00R/WFORCE_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69230Force Local Receiver Preset Hint.Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0R/WRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69238Reserved for future use.23210x0RFORCE_LOCAL_TX_PRESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69254Force Local Transmitter Preset.Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.27240x0R/WFORCE_LOCAL_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69268Force Local Transmitter Coefficient Enable.Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSORNote: This register field is sticky.28280x0R/WFORCE_LOCAL_RX_HINT_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69283Force Local Receiver Preset Hint Enable.Enables the FORCE_LOCAL_RX_HINT field.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.29290x0R/WFORCE_LOCAL_TX_PRESET_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69298Force Local Transmitter Preset Enable.Enables the FORCE_LOCAL_TX_PRESET field.If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69306Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGSD_EQ_CONTROL3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr693910xD8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REGSilicon Debug EQ Control 3.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_REMOTE_TX_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69329Force Remote Transmitter Pre-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.500x00R/WFORCE_REMOTE_TX_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69343Force Remote Transmitter Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.1160x00R/WFORCE_REMOTE_TX_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69357Force Remote Transmitter Post-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.17120x00R/WRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69365Reserved for future use.27180x000RFORCE_REMOTE_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69382Force Remote Transmitter Coefficient Enable.Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSORThis function can only be used when GEN3_EQ_FB_MODE = 0000b(Direction Change)Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69390Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGSD_EQ_STATUS1_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr695350xE0R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REGSilicon Debug EQ Status 1.This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENTFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_SEQUENCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69421EQ Sequence.Indicates that the controller is starting the equalization sequence.Note: This register field is sticky.000x0REQ_CONVERGENCE_INFOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69440EQ Convergence Info.Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: ReservedThis bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.210x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69447Reserved for future use.330x0REQ_RULEA_VIOLATIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69468EQ Rule A Violation.Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.440x0REQ_RULEB_VIOLATIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69489EQ Rule B Violation.Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.550x0REQ_RULEC_VIOLATIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69510EQ Rule C Violation.Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.660x0REQ_REJECT_EVENTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69527EQ Reject Event.Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.770x0RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69534Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGSD_EQ_STATUS2_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr696230xE4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REGSilicon Debug EQ Status 2.This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LOCAL_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69560EQ Local Pre-Cursor.Indicates Local pre cursor coefficient value.Note: This register field is sticky.500x00REQ_LOCAL_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69573EQ Local Cursor.Indicates Local cursor coefficient value.Note: This register field is sticky.1160x00REQ_LOCAL_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69586EQ Local Post-Cursor.Indicates Local post cursor coefficient value.Note: This register field is sticky.17120x00REQ_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69602EQ Local Receiver Preset Hint.Indicates Local Receiver Preset Hint value.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69609Reserved for future use.23210x0REQ_LOCAL_FOM_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69622EQ Local Figure of Merit.Indicates Local maximum Figure of Merit value.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGSD_EQ_STATUS3_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr697080xE8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REGSilicon Debug EQ Status 3.This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_REMOTE_PRE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69648EQ Remote Pre-Cursor.Indicates Remote pre cursor coefficient value.Note: This register field is sticky.500x00REQ_REMOTE_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69661EQ Remote Cursor.Indicates Remote cursor coefficient value.Note: This register field is sticky.1160x00REQ_REMOTE_POST_CURSORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69674EQ Remote Post-Cursor.Indicates Remote post cursor coefficient value.Note: This register field is sticky.17120x00REQ_REMOTE_LFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69687EQ Remote LF.Indicates Remote LF value.Note: This register field is sticky.23180x00REQ_REMOTE_FSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69700EQ Remote FS.Indicates Remote FS value.Note: This register field is sticky.29240x00RRSVDP_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69707Reserved for future use.31300x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAPPF0_VSECRAS_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr707620x3C4R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAPPF RAS Datapath Protection Capability Structure (VSEC)registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFRASDP_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr697690x0R0x3fc1000bPE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFFPCIe Extended capability ID, Capability version and Next capability offset.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69736PCI Express Extended Capability ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69752Capability Version.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69768Next Capability Offset.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3fcRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFRASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr698120x4R0x03810001PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFFVendor Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69787VSEC ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1500x0001RVSEC_REVPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69799VSEC Rev.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.19160x1RVSEC_LENGTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69811VSEC Length.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.31200x038RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFRASDP_ERROR_PROT_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70018ECC error correction control0x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFFECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.falsefalsefalsefalseERROR_PROT_DISABLE_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69836Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.000x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_MASTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69847Error correction disable for AXI bridge master completion buffer.Note: This register field is sticky.110x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69858Error correction disable for AXI bridge outbound request path.Note: This register field is sticky.220x0R/WERROR_PROT_DISABLE_DMA_WRITEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69868Error correction disable for DMA write engine.Note: This register field is sticky.330x0R/WERROR_PROT_DISABLE_LAYER2_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69878Error correction disable for layer 2 Tx path.Note: This register field is sticky.440x0R/WERROR_PROT_DISABLE_LAYER3_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69888Error correction disable for layer 3 Tx path.Note: This register field is sticky.550x0R/WERROR_PROT_DISABLE_ADM_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69898Error correction disable for Adm Tx path.Note: This register field is sticky.660x0R/WERROR_PROT_DISABLE_CXS_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69908Error correction disable for CXS Rx path (PCIe Tx path).Note: This register field is sticky.770x0R/WERROR_PROT_DISABLE_DTIM_TXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69918Error correction disable for DTIM Tx path.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69926Reserved for future use.1590x00RERROR_PROT_DISABLE_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69936Global error correction disable for all Rx layers.Note: This register field is sticky.16160x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69948Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.17170x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUESTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69959Error correction disable for AXI bridge inbound request path.Note: This register field is sticky.18180x0R/WERROR_PROT_DISABLE_DMA_READPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69969Error correction disable for DMA read engine.Note: This register field is sticky.19190x0R/WERROR_PROT_DISABLE_LAYER2_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69979Error correction disable for layer 2 Rx path.Note: This register field is sticky.20200x0R/WERROR_PROT_DISABLE_LAYER3_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69989Error correction disable for layer 3 Rx path.Note: This register field is sticky.21210x0R/WERROR_PROT_DISABLE_ADM_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr69999Error correction disable for ADM Rx path.Note: This register field is sticky.22220x0R/WERROR_PROT_DISABLE_CXS_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70009Error correction disable for CXS Tx path (PCIe Rx path).Note: This register field is sticky.23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70017Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFRASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr701050xCR/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFFCorrected error (1-bit ECC) counter selection and control.This is a viewport control register.Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70035Clear all correctable error counters.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70043Reserved for future use.310x0RCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70055Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70063Reserved for future use.1950x0000RCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70089Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70104Counter selection.This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFRASDP_CORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr701670x10R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFFCorrected error (1-bit ECC) counter data.This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseCORR_COUNTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70121Current corrected error count for the selected counter.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70128Reserved for future use.1980x000RCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70155Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70166Counter selection.Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFRASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr702580x14R/W0x00000010PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFFUncorrected error (2-bit ECC and parity) counter selection and control.This is a viewport control register.Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseUNCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70187Clear uncorrectable errors counters.When asserted causes all counters tracking the uncorrectable errors to be cleared.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70195Reserved for future use.310x0RUNCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70207Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70215Reserved for future use.1950x0000RUNCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70241Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WUNCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70257Counter selection.This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFRASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr703210x18R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFFUncorrected error (2-bit ECC and parity) counter data.This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseUNCORR_COUNTERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70275Current uncorrected error count for the selected counter700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70282Reserved for future use.1980x000RUNCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70309Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RUNCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70320Counter selection.Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFRASDP_ERROR_INJ_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70401Error injection control0x1CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFFError injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occursfalsefalsefalsefalseERROR_INJ_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70339Error injection global enable.When set enables the error insertion logic.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70347Reserved for future use.310x0RERROR_INJ_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70358Error injection type: - 0: none - 1: 1-bit - 2: 2-bit540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70366Reserved for future use.760x0RERROR_INJ_COUNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70379Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected1580x00R/WERROR_INJ_LOCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70392Error injection location.Selects where error injection takes place.You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70400Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFRASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70508Corrected errors locations.0x20R0x00d000d0PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFFCorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70416Reserved for future use.300x0RREG_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70443Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70458Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70465Reserved for future use.19160x0RREG_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70492Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70507Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFRASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70615Uncorrected errors locations.0x24R0x00d000d0PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFFUncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70523Reserved for future use.300x0RREG_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70550Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70565Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70572Reserved for future use.19160x0RREG_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70599Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70614Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFRASDP_ERROR_MODE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70659RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error.0x28R/W0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFFRASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them.For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70639Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error.Note: This register field is sticky.000x1R/WAUTO_LINK_DOWN_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70650Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.Note: This register field is sticky.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70658Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFRASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70687Exit RASDP error mode.0x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFFExit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70678Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70686Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFRASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70724RAM Address where a corrected error (1-bit ECC) has been detected.0x30R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFFRAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70706RAM Address where a corrected error (1-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70713Reserved for future use.27270x0RRAM_INDEX_CORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70723RAM index where a corrected error (1-bit ECC) has been detected.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFRASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70761RAM Address where an uncorrected error (2-bit ECC) has been detected.0x34R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFFRAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70743RAM Address where an uncorrected error (2-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70750Reserved for future use.27270x0RRAM_INDEX_UNCORR_ERRORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70760RAM index where an uncorrected error (2-bit ECC) has been detected.31280x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAPPF0_DLINK_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr709420x3FCRPE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAPPF DLINK Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFDATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70836This register provides capbility ID, capability version and next offset value.0x0R0x00010025PE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFFData Link Feature Extended Capability Header.This register provides capbility ID, capability version and next offset value.falsefalsefalsefalseDLINK_EXT_CAP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70792Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for Data Link Feature is 0025h.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0025RDLINK_CAP_VERSIONPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70809Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RDLINK_NEXT_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70835Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFDATA_LINK_FEATURE_CAP_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70897This register provides description about extended feature.0x4R0x80000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFFData Link Feature Capabilities.This register provides description about extended feature.falsefalsefalsefalseSCALED_FLOW_CNTL_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70860Local Scaled Flow Control Supported.Bit 0 – Local Scaled Flow Control Supported. Bit 22:1 – RsvdP.Bits associated with features that this Port is capable of supporting are HwInit, defaulting to 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 000x1RFUTURE_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70874Local Future Data Link Feature Supported.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.2210x000000RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70881Reserved for future use.30230x00RDL_FEATURE_EXCHANGE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70896Data Link Feature Exchange Enable.If Set, this bit indicates that this Port will enter the DL_Feature negotiation state. Default is 1b.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFDATA_LINK_FEATURE_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr70941This Registor privides status of the capability of data link feature.0x8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFFData Link Feature Status Register.This Registor privides status of the capability of data link feature.falsefalsefalsefalseREMOTE_DATA_LINK_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70918Remote Data Link Feature SupportedFeatures Currently defined are: Bit 0 - Remote Scaled Flow Control Supported.Other Bits are undefined. Default value is 00 0000h.2200x000000RRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70925Reserved for future use.30230x00RDATA_LINK_FEATURE_STATUS_VALIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70940Remote Data Link Feature Supported Valid.This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature (see Section 3.2.1) and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields arefield is meaningful. This bit is Cleared on entry to state DL_Inactive.Default is 0b.31310x0RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGICPF0_PORT_LOGICPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr767830x700R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGICPort LogicregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFACK_LATENCY_TIMER_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr709990x0R/W0x0c23040bPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFFAck Latency Timer and Replay Timer Register.falsefalsefalsefalseROUND_TRIP_LATENCY_TIME_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70974Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling".You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification.The limit must reflect the round trip latency from requester to completer.If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.1500x040bR/WREPLAY_TIME_LIMITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr70998Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay".You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification.If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.31160x0c23R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFVENDOR_SPEC_DLLP_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr710210x4R/W0xffffffffPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFFVendor Specific DLLP Register.falsefalsefalsefalseVENDOR_SPEC_DLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71020Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP.Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8] = Payload (24 bits)The dllp type is in bits [7:0] while the remainder is the vendor defined payload.Note: This register field is sticky.3100xffffffffR/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPORT_FORCE_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr711150x8R/W0x00800004PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PORT_FORCE_OFFPort Force Link Register.falsefalsefalsefalseLINK_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71033Link Number. Not used for endpoint. Not used for M-PCIe.Note: This register field is sticky.700x04R/WFORCED_LTSSMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71046Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link).Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71054Reserved for future use.14120x0RFORCE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71073Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced Link Command field.This is a self-clearing register field. Reading from this register field always returns a "0".15150x0WLINK_STATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71085Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link).LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71093Reserved for future use.22220x0RDO_DESKEW_FOR_SRISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71106Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, EIEOS to Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS is set to 1.Note: This register field is sticky.23230x1R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71114Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFACK_F_ASPM_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr712420xCR/W0x1bc8c800PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFFAck Frequency and L0-L1 ASPM Control Register.falsefalsefalsefalseACK_FREQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71143Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK request for every TLP that it receives. The controller waits until the ACK Latency Timer expires, then converts the current low-priority ACK request to a high-priority ACK request and schedules the DLLP for transmission to the remote link partner. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs if the ACK Latency Timer expires, but never later.For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".Note: This register field is sticky.700x00R/WACK_N_FTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71159N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255.The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.1580xc8R/WCOMMON_CLK_N_FTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71185Common Clock N_FTS. This is the N_FTS when common clock is used.The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYThe controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 23160xc8RL0S_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71202L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 usThis field is applicable to STALL while in L0 for M-PCIe.Note: This register field is sticky.26240x3R/WL1_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71221L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 usNote: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.Note: This register field is sticky.29270x3R/WENTER_ASPMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71233ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71241Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPORT_LINK_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr714380x10R/W0x00000120PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFFPort Link Control Register.falsefalsefalsefalseVENDOR_SPECIFIC_DLLP_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71259Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.Reading from this self-clearing register field always returns a '0'.000x0R/W1CSCRAMBLE_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71268Scramble Disable. Turns off data scrambling.Note: This register field is sticky.110x0R/WLOOPBACK_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71284Loopback Enable. Turns on loopback. For more details, see "Loopback".For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration).M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.Note: This register field is sticky.220x0R/WRESET_ASSERTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71294Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).Note: This register field is sticky.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71302Reserved for future use.440x0RDLL_LINK_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71313DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit InitFC DLLPs and does not establish a link.Note: This register field is sticky.550x1R/WLINK_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71322LINK_DISABLE is an internally reserved field. Do not use.Note: This register field is sticky.660x0R/WFAST_LINK_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71349Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster.The default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF register.Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'.For more details, see the "Fast Link Simulation Mode" section in the "Integrating the Controller with the PHY or Application RTL or Verification IP" chapter of the User Guide.For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).Note: This register field is sticky.770x0R/WLINK_RATEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71358LINK_RATE is an internally reserved field. Do not use.Note: This register field is sticky.1180x1R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71366Reserved for future use.15120x0RLINK_CAPABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71390Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported)This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.2116R/W--23220x0rBEACON_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71399BEACON_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.24240x0R/WCORRUPT_LCRC_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71409CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WEXTENDED_SYNCHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71419EXTENDED_SYNCH is an internally reserved field. Do not use.Note: This register field is sticky.26260x0R/WTRANSMIT_LANE_REVERSALE_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71429TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.27270x0R/WRSVDP_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71437Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFLANE_SKEW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr715190x14R/W0x3c000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_LANE_SKEW_OFFLane Skew Register.falsefalsefalsefalseINSERT_LANE_SKEWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71451INSERT_LANE_SKEW is an internally reserved field. Do not use.Note: This register field is sticky.2300x000000R/WFLOW_CTRL_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71461Flow Control Disable. Prevents the controller from sending FC DLLPs.Note: This register field is sticky.24240x0R/WACK_NAK_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71471Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs.Note: This register field is sticky.25250x0R/WELASTIC_BUFFER_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71482Selects Elasticity Buffer operating mode:0: Nominal Half Full Buffer mode1: Nominal Empty Buffer ModeNote: This register field is sticky.26260x1R/WIMPLEMENT_NUM_LANESPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71508Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanesThe number of lanes to be used when in Loopback Master. The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field.The controller will transition from Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field.Note: This register field is sticky.30270x7R/WDISABLE_LANE_TO_LANE_DESKEWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71518Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFTIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr716160x18R/W0x40000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFFTimer Control and Max Function Number Register.falsefalsefalsefalseMAX_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71533Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).Note: This register field is sticky.700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71541Reserved for future use.1380x00RTIMER_MOD_REPLAY_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71561Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.At Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.Note: This register field is sticky.1814R/WTIMER_MOD_ACK_NAKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71575Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.Note: This register field is sticky.23190x00R/WUPDATE_FREQ_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71585UPDATE_FREQ_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.28240x00R/WFAST_LINK_SCALING_FACTORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71607Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us)Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.*a. When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, 2ms timer is 4us and 3ms timer is 6us.Not used for M-PCIe. Note: This register field is sticky.30290x2R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71615Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFSYMBOL_TIMER_FILTER_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr717730x1CR/W0x00000140PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFFSymbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseSKP_INT_VALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71655SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP ordered sets once every 1537 symbol times.The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NBYou need to set this field again if necessary when 2K_PPM_DISABLED is changed.Note: This register field is sticky.1000x140R/WEIDLE_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71664EIDLE_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.14110x0R/WDISABLE_FC_WD_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71673Disable FC Watchdog Timer.Note: This register field is sticky.15150x0R/WMASK_RADM_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71772Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received[30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received[29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII.[28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW.[27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up[26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions[25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions[24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions[23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions[22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions[21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions[20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC[19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number.[18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR[17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native controller always passes poisoned completions to your application except when you are using the DMA read channel.[16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as URNote: This register field is sticky.31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFFILTER_MASK_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr718340x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_FILTER_MASK_2_OFFFilter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseMASK_RADM_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71833Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31:10]: Reserved[9]: CX_FLT_MASK_CPL_IN_LUT_CHECK - 0: Disable masking of checking if the tag of CPL is registered in LUT - 1: Enable masking of checking if the tag of CPL is registered in LUT[8]: CX_FLT_MASK_POIS_ERROR_REPORTING - 0: Disable masking of error reporting for Poisoned TLPs - 1: Enable masking of error reporting for Poisoned TLPs[7]: CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the SYMBOL_TIMER_FILTER_1_OFF register is set to '1'.[6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE[5]: CX_FLT_UNMASK_UR_POIS_TRGT0 - 0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination[4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass through - 1: Drop LN Messages silently[3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller Filter to handle flush request - 1: Enable controller Filter to handle flush request[2]: CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP abort for unexpected completion[1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped silently - 1: Vendor MSG Type 1 not dropped[0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0 dropped with UR error reporting - 1: Vendor MSG Type 0 not droppedNote: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr718680x24R/W0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA Multiple Outbound Decomposed NP SubRequests Control Register.falsefalsefalsefalseOB_RD_SPLIT_BURST_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71859Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to "0" disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge Ordering" in the AXI chapter of the Databook.You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device (or switch) is reordering completions that have different tags.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71867Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPL_DEBUG0_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr718810x28RPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PL_DEBUG0_OFFDebug Register 0falsefalsefalsefalseDEB_REG_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71880The value on cxpl_debug_info[31:0].310RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPL_DEBUG1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr718940x2CRPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PL_DEBUG1_OFFDebug Register 1falsefalsefalsefalseDEB_REG_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71893The value on cxpl_debug_info[63:32].310RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFTX_P_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr719480x30R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFFTransmit Posted FC Credit StatusfalsefalsefalsefalseTX_P_DATA_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71919Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_P_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71940Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_P_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71947Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFTX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr720020x34R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFFTransmit Non-Posted FC Credit StatusfalsefalsefalsefalseTX_NP_DATA_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71973Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_NP_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr71994Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_NP_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72001Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFTX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr720560x38R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFFTransmit Completion FC Credit StatusfalsefalsefalsefalseTX_CPL_DATA_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72027Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_CPL_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72048Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_CPL_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72055Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFQUEUE_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr721600x3CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_QUEUE_STATUS_OFFQueue StatusfalsefalsefalsefalseRX_TLP_FC_CREDIT_NON_RETURNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72073Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.000x0RTX_RETRY_BUFFER_NEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72084Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.110x0RRX_QUEUE_NON_EMPTYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72095Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.220x0RRX_QUEUE_OVERFLOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72106Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue.330x0R/W1CRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72114Reserved for future use.1240x000RRX_SERIALIZATION_Q_NON_EMPTYPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72125Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.13130x0R--15140x0rTIMER_MOD_FLOW_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72138FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the controller calculates according to the PCIe specification. For more details, see "Flow Control".Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72146Reserved for future use.30290x0RTIMER_MOD_FLOW_CONTROL_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72159FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the controller calculates according to the PCIe specification.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFVC_TX_ARBI_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr722090x40R0x0000000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFFVC Transmit Arbitration Register 1falsefalsefalsefalseWRR_WEIGHT_VC_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72175WRR Weight for VC0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 700x0fRWRR_WEIGHT_VC_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72186WRR Weight for VC1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 1580x00RWRR_WEIGHT_VC_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72197WRR Weight for VC2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 23160x00RWRR_WEIGHT_VC_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72208WRR Weight for VC3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFVC_TX_ARBI_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr722580x44R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFFVC Transmit Arbitration Register 2falsefalsefalsefalseWRR_WEIGHT_VC_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72224WRR Weight for VC4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 700x00RWRR_WEIGHT_VC_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72235WRR Weight for VC5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 1580x00RWRR_WEIGHT_VC_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72246WRR Weight for VC6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 23160x00RWRR_WEIGHT_VC_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72257WRR Weight for VC7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFVC0_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr723620x48R/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFFSegmented-Buffer VC0 Posted Receive Queue Control.falsefalsefalsefalseVC0_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72275VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC0_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72289VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72298Reserved.Note: This register field is sticky.20200x0R/WVC0_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72307Reserved.Note: This register field is sticky.23210x1R/WVC0_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72317VC0 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72327VC0 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72336Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72348TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WVC_ORDERING_RX_QPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72361VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robinNote: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFVC0_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr724410x4CR/W0x06260060PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFFSegmented-Buffer VC0 Non-Posted Receive Queue Control.falsefalsefalsefalseVC0_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72379VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x060R/WVC0_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72393VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72402Reserved.Note: This register field is sticky.20200x0R/WVC0_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72411Reserved.Note: This register field is sticky.23210x1R/WVC0_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72421VC0 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72431VC0 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72440Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFVC0_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr725200x50R/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC0 Completion Receive Queue Control.falsefalsefalsefalseVC0_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72458VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC0_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72472VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72481Reserved.Note: This register field is sticky.20200x0R/WVC0_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72490Reserved.Note: This register field is sticky.23210x1R/WVC0_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72500VC0 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC0_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72510VC0 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72519Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFVC1_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr726200x54R/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC1_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72537VC1 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC1_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72551VC1 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72560Reserved.Note: This register field is sticky.20200x0R/WVC1_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72569Reserved.Note: This register field is sticky.23210x1R/WVC1_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72579VC1 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72589VC1 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72598Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72610TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72619Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFVC1_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr726990x58R/W0x06260001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC1_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72637VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC1_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72651VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72660Reserved.Note: This register field is sticky.20200x0R/WVC1_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72669Reserved.Note: This register field is sticky.23210x1R/WVC1_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72679VC1 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72689VC1 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72698Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFVC1_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr727780x5CR/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC1_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72716VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC1_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72730VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72739Reserved.Note: This register field is sticky.20200x0R/WVC1_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72748Reserved.Note: This register field is sticky.23210x1R/WVC1_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72758VC1 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC1_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72768VC1 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72777Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFVC2_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr728780x60R/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC2_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72795VC2 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC2_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72809VC2 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72818Reserved.Note: This register field is sticky.20200x0R/WVC2_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72827Reserved.Note: This register field is sticky.23210x1R/WVC2_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72837VC2 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72847VC2 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72856Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72868TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72877Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFVC2_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr729570x64R/W0x06260001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC2_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72895VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC2_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72909VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72918Reserved.Note: This register field is sticky.20200x0R/WVC2_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72927Reserved.Note: This register field is sticky.23210x1R/WVC2_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72937VC2 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72947VC2 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72956Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFVC2_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr730360x68R/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC2_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72974VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC2_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72988VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr72997Reserved.Note: This register field is sticky.20200x0R/WVC2_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73006Reserved.Note: This register field is sticky.23210x1R/WVC2_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73016VC2 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC2_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73026VC2 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73035Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFVC3_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr731360x6CR/W0x462602e0PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC3_P_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73053VC3 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC3_P_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73067VC3 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73076Reserved.Note: This register field is sticky.20200x0R/WVC3_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73085Reserved.Note: This register field is sticky.23210x1R/WVC3_P_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73095VC3 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_P_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73105VC3 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73114Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73126TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73135Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFVC3_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr732150x70R/W0x06260001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC3_NP_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73153VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC3_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73167VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73176Reserved.Note: This register field is sticky.20200x0R/WVC3_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73185Reserved.Note: This register field is sticky.23210x1R/WVC3_NP_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73195VC3 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_NP_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73205VC3 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73214Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFVC3_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr732940x74R/W0x06200000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC3_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73232VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC3_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73246VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73255Reserved.Note: This register field is sticky.20200x0R/WVC3_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73264Reserved.Note: This register field is sticky.23210x1R/WVC3_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73274VC3 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC3_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73284VC3 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73293Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFGEN2_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr73578Link Width and Speed Change Control Register.0x10CR/W0x000108c8PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN2_CTRL_OFFThis register is used to control various functions of the controller related to link training, lane reversal, and equalization.falsefalsefalsefalseFAST_TRAINING_SEQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73321Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.700xc8R/WNUM_OF_LANESPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73361Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - ..When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.1280x08R/WPRE_DET_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73411Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.Note: This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.15130x0R/WfalsetruefalseLANE00x0Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detectedLANE10x1Connect logical Lane0 to physical lane 1LANE150x4Connect logical Lane0 to physical lane 15LANE30x2Connect logical Lane0 to physical lane 3LANE70x3connect logical lane0 to physical lane 7AUTO_LANE_FLIP_CTRL_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73429Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.16160x1R/WDIRECT_SPEED_CHANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73462Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed.When the speed change occurs, the controller will clear the contents of this field; and a read to this field by your software will return a "0".To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this fieldIf you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the controller clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 17170x0R/WCONFIG_PHY_TX_CHANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73479Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low SwingThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.18180x0R/WCONFIG_TX_COMP_RXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73494Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1").This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WSEL_DEEMPHASISPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73510Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dBThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.20200x0R/WGEN1_EI_INFERENCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73528Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical IdleNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73536Reserved for future use.23220x0RLANE_UNDER_TESTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73552The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.27240x0R/W--29280x0rFORCE_LANE_FLIPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73569Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73577Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPHY_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr736020x110RPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PHY_STATUS_OFFPHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.falsefalsefalsefalsePHY_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73601PHY Status. Data received directly from the phy_cfg_status bus.These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband status signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.310RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPHY_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr736240x114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PHY_CONTROL_OFFPHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.falsefalsefalsefalsePHY_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73623PHY Control. Data sent directly to the cfg_phy_control bus.These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband control signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFTRGT_MAP_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr736830x11CR/W0x0000006fPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFFProgrammable Target Map Control Register.falsefalsefalsefalseTARGET_MAP_PFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73637Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.500x2fR/WTARGET_MAP_ROMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73648Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.660x1R/W--1270x0rTARGET_MAP_RESERVED_13_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73660Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) 15130x0RTARGET_MAP_INDEXPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73670The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits.20160x00R/WTARGET_MAP_RESERVED_21_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73682Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) 31210x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFMSI_CTRL_ADDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr737030x120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFFIntegrated MSI Reception Module (iMRM) Address Register.falsefalsefalsefalseMSI_CTRL_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73702Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination.Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and also to see if it satisfies the definition of an MSI interrupt request. When these conditions are satisfied the Memory Write request is marked as an MSI request.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFMSI_CTRL_UPPER_ADDR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr737190x124R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFFIntegrated MSI Reception Module Upper Address Register.falsefalsefalsefalseMSI_CTRL_UPPER_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73718Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFMSI_CTRL_INT_0_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr737360x128R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_0_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73735MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFMSI_CTRL_INT_0_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr737540x12CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_0_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73753MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFMSI_CTRL_INT_0_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr737720x130R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_0_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73771MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFMSI_CTRL_INT_1_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr737890x134R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_1_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73788MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFMSI_CTRL_INT_1_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr738070x138R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_1_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73806MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFMSI_CTRL_INT_1_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr738250x13CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_1_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73824MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFMSI_CTRL_INT_2_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr738420x140R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_2_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73841MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFMSI_CTRL_INT_2_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr738600x144R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_2_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73859MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFMSI_CTRL_INT_2_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr738780x148R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_2_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73877MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFMSI_CTRL_INT_3_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr738950x14CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_3_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73894MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFMSI_CTRL_INT_3_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr739130x150R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_3_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73912MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFMSI_CTRL_INT_3_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr739310x154R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_3_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73930MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFMSI_CTRL_INT_4_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr739480x158R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_4_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73947MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFMSI_CTRL_INT_4_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr739660x15CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_4_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73965MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFMSI_CTRL_INT_4_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr739840x160R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_4_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr73983MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFMSI_CTRL_INT_5_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr740010x164R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_5_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74000MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFMSI_CTRL_INT_5_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr740190x168R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_5_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74018MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFMSI_CTRL_INT_5_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr740370x16CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_5_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74036MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFMSI_CTRL_INT_6_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr740540x170R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_6_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74053MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFMSI_CTRL_INT_6_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr740720x174R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_6_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74071MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFMSI_CTRL_INT_6_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr740900x178R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_6_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74089MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFMSI_CTRL_INT_7_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr741070x17CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_7_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74106MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFMSI_CTRL_INT_7_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr741250x180R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_7_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74124MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFMSI_CTRL_INT_7_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr741430x184R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_7_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74142MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFMSI_GPIO_IO_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr741570x188R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSI_GPIO_IO_OFFIntegrated MSI Reception Module General Purpose IO Register.falsefalsefalsefalseMSI_GPIO_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74156MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0]Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFCLOCK_GATING_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr742250x18CR/W0x00000003PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFFThis register enables you to disable dynamic clock gating. By default dynamic clock gating is on, allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module, DWC_pcie_clk_rst.v, and is initiated by the controllers clock enable signals. The following modules support dynamic clock gating: - AXI Bridge - RADMfalsefalsefalsefalseRADM_CLK_GATING_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74189RADM Clock Gating Enable. This register, if set, enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock, radm_clk_g, to the RADM and is enabled when the controllers clock enable signal, en_radm_clk_g, is asserted. The RADM clock is a gated version of the controller clock, core_clk. The controller de-asserts en_radm_clk_g when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. - 0: Disable - 1: Enable (default)Note: This register field is sticky.000x1R/WAXI_CLK_GATING_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74216AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock, the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock, mstr_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, mstr_aclk_active, is asserted. For the AXI Slave this module provides the gated clock, slv_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, slv_aclk_active, is asserted. If the AXI DBI Slave is enabled (DBI_4SLAVE_POPULATED=1) the module provides the gated clock, dbi_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, dbi_aclk_active, is asserted. The controller de-asserts the clock enable signals when the respective AXI Master/Slave interfaces are idle. - 0: Disable - 1: Enable (default)Note: This register field is sticky.110x1R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74224Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFGEN3_RELATED_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr745700x190R/W0x00402001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN3_RELATED_OFFGen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_ZRXDC_NONCOMPLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74260Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rates.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74268Reserved for future use.710x00RDISABLE_SCRAMBLER_GEN_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74283Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY).Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.880x0R/WEQ_PHASE_2_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74304Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.990x0R/WEQ_EIEOS_CNTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74318Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.10100x0R/WEQ_REDOPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74338Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is infinite or you do not want eq requests and redo, setting this bit to 1 will stop the EQ requests and EQ redo so that the link can go ahead to L0 state for packet trasmissions.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.11110x0R/WRXEQ_PH01_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74369Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.12120x0R/WRXEQ_RGRDLESS_RXTSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74395When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.13130x1R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74403Reserved for future use.15140x0RGEN3_EQUALIZATION_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74417Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.16160x0R/WGEN3_DLLP_XMT_DELAY_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74431DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.17170x0R/WGEN3_DC_BALANCE_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74443DC Balance Disable. Disable DC Balance feature.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.18180x0R/WRSVDP_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74451Reserved for future use.20190x0RAUTO_EQ_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74478Autonomous Equalization Disable. When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.21210x0R/WUSP_SEND_8GT_EQ_TS2_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74505Upstream Port Send 8GT/s or 16GT/s EQ TS2 Disable. The base spec defines that USP can optionally send 8GT or 16GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 or Gen5 Data Rate. If this register set to 0, USP sends 8GT or 16GT EQ TS2. If this register set to 1, USP does not send 8GT or 16GT EQ TS2. This applies to upstream ports only. No Function for downstream ports.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. Value after reset in Gen4/Gen5 is 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: see description Note: This register field is sticky.22220x1R/WGEN3_EQ_INVREQ_EVAL_DIFF_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74520Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.23230x0R/WRATE_SHADOW_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74561Rate Shadow Select. This register value decide the Data Rate of shadow register. - 00b: Gen3 Data Rate is selected for shadow register. - 01b: Gen4 Data Rate is selected for shadow register. - 10b: Gen5 Data Rate is selected for shadow register. - 11b: Reserved.The following shadow registers are controlled by this register. - GEN3_RELATED_OFF[9] EQ_PHASE_2_3 - GEN3_RELATED_OFF[12] RXEQ_PH01_EN - GEN3_RELATED_OFF[19] RE_EQ_REQUEST_ENABLE - GEN3_RELATED_OFF[21] AUTO_EQ_DISABLE - GEN3_RELATED_OFF[22] USP_SEND_8GT_EQ_TS2_DISABLE - GEN3_EQ_LOCAL_FS_LF_OFF[5:0] GEN3_EQ_LOCAL_LF - GEN3_EQ_LOCAL_FS_LF_OFF[11:6] GEN3_EQ_LOCAL_FS - GEN3_EQ_PSET_COEFF_MAP_0[5:0] GEN3_EQ_PRE_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[11:6] GEN3_EQ_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[17:12] GEN3_EQ_POSET_CURSOR_PSET - GEN3_EQ_CONTROL_OFF[3:0] GEN3_EQ_FB_MODE - GEN3_EQ_CONTROL_OFF[4] GEN3_EQ_PHASE23_EXIT_MODE - GEN3_EQ_CONTROL_OFF[5] GEN3_EQ_EVAL_2MS_DISABLE - GEN3_EQ_CONTROL_OFF[23:8] GEN3_EQ_PSET_REQ_VEC - GEN3_EQ_CONTROL_OFF[24] GEN3_EQ_FOM_INC_INITIAL_EVAL - GEN3_EQ_CONTROL_OFF[25] GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[4:0] GEN3_EQ_FMDC_T_MIN_PHASE23 - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[9:5] GEN3_EQ_FMDC_N_EVALS - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[13:10] GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[17:14] GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTANote: This register field is sticky.25240x0R/WRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74569Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFGEN3_EQ_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr748020x1A8R/W0x05039f71PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFFGen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_EQ_FB_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74598Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: ReservedNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.300x1R/WGEN3_EQ_PHASE23_EXIT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74645Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2"For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLockWhen optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2"Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.440x1R/WGEN3_EQ_EVAL_2MS_DISABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74669Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.550x1R/WGEN3_LOWER_RATE_EQ_REDO_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74683Support EQ redo and lower rate change: - 0: not support - 1: supportNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.660x1R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74691Reserved for future use.770x0RGEN3_EQ_PSET_REQ_VECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74746Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: ReservedNote: You must contact your PHY vendor to ensure 24 ms timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.2380x039fR/WGEN3_EQ_FOM_INC_INITIAL_EVALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74766Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: IncludeNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.24240x1R/WGEN3_EQ_PSET_REQ_AS_COEFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74777GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WGEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74793Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: requestNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.26260x1R/WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74801Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr749080x1ACR/W0x00000040PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes.falsefalsefalsefalseGEN3_EQ_FMDC_T_MIN_PHASE23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74833Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients.Allowed values 0,1,...,24.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.400x00R/WGEN3_EQ_FMDC_N_EVALSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74860Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found.Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH.When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.950x02R/WGEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74880Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth.Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.13100x0R/WGEN3_EQ_FMDC_MAX_POST_CUSROR_DELTAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74899Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.17140x0R/WRSVDP_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74907Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFORDER_RULE_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr749420x1B4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFFOrder Rule Control Register.falsefalsefalsefalseNP_PASS_PPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74922Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P700x00R/WCPL_PASS_PPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74933Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P1580x00R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74941Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPIPE_LOOPBACK_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr749980x1B8R/W0x000000ffPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFFPIPE Loopback Control Register.falsefalsefalsefalseLPBK_RXVALIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74954LPBK_RXVALID is an internally reserved field. Do not use.Note: This register field is sticky.1500x00ffR/WRXSTATUS_LANEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74963RXSTATUS_LANE is an internally reserved field. Do not use.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74971Reserved for future use.23220x0RRXSTATUS_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74980RXSTATUS_VALUE is an internally reserved field. Do not use.2624WRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74988Reserved for future use.30270x0RPIPE_LOOPBACKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr74997PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFMISC_CONTROL_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr751920x1BCR/W0x0007ff48PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MISC_CONTROL_1_OFFDBI Read-Only Write Enable Register.falsefalsefalsefalseDBI_RO_WR_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75016Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'.For more details, see "Writing to Read-Only Registers" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.000x0R/WDEFAULT_TARGETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75037Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status is generated for non-posted requests. - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application.For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.110x0R/WUR_CA_MASK_4_TRGT1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75051When this field is set to '1', the controller suppresses error logging, error message generation, and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is, when DEFAULT_TARGET =1). For more details, see "Advanced Error Handling For Received TLPs" chapter of the Databook.Note: This register field is sticky.220x0R/WSIMPLIFIED_REPLAY_TIMERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75070Enables Simplified Replay Timer (Gen4). For more details, see "Transmit Replay" in "Transmit TLP Processing" section in the "Controller Operations" chapter of the Databook.Simplified Replay Timer can have the following Values: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b.The Simplified Replay Timer value must not be changed while the link is in use.Note: This register field is sticky.330x1R/WDISABLE_AUTO_LTR_CLR_MSGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75088Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear message.For more details, see "Latency Tolerance Reporting (LTR) Message Generation[EP Mode]" in "Message Generation" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.440x0R/WARI_DEVICE_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75098When ARI is enabled, this field enables use of the device ID.Note: This register field is sticky.550x0R/WCPLQ_MNG_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75108This field enables the Completion Queue Management feature.Note: This register field is sticky.660x1R/WCFG_TLP_BYPASS_EN_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75127Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG - 1: Configuration TLPs are routed according to the setting of CONFIG_LIMIT_REGNote: When app_req_retry_en is asserted, the setting of this field is ignored.Note: This register field is sticky.770x0R/WCONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75148Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of TARGET_ABOVE_CONFIG_LIMIT_REG field.Your application must set a proper value for this field based on your extended configuration registers. For more details, see the "CDM/ELBI Register Space Access Through CFG Request" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.1780x3ffR/WTARGET_ABOVE_CONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75161Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1Note: This register field is sticky.19180x1R/WP2P_TRACK_CPL_TO_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75172Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reportingNote: This register field is sticky.20200x0R/WP2P_ERR_RPT_CTRLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75183Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completionNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75191Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFMULTI_LANE_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr752660x1C0R/W0x00000080PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFFUpConfigure Multi-lane Control Register.Used when upsizing or downsizing the link width through Configuration state without bringing the link down.For more details, see the "Link Establishment" section in the "ControllerOperations" chapter of the Databook.falsefalsefalsefalseTARGET_LINK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75219Target Link Width.Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32This field is reserved (fixed to '0') for M-PCIe.500x00R/WDIRECT_LINK_WIDTH_CHANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75242Directed Link Width Change.The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure or autonomous width downsizing in the Configuration state.The controller self-clears this field when the controller accepts this request.This field is reserved (fixed to '0') for M-PCIe.660x0R/WUPCONFIGURE_SUPPORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75257Upconfigure Support.The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.770x1R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75265Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPHY_INTEROP_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr753820x1C4R/W0x00000a44PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFFPHY Interoperability Control Register.falsefalsefalsefalseRXSTANDBY_CONTROLPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75295Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus HandshakeThis field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.600x44R/WRSVDP_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75303Reserved for future use.770x0RL1SUB_EXIT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75320L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. - 0: Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1.Note: This register field is sticky.880x0R/WL1_NOWAIT_P1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75341L1 entry control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Controller waits for the PHY to acknowledge transition to P1 before entering L1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register field is sticky.990x1RL1_CLK_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75358L1 Clock control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1.Note: This register field is sticky.10100x0R/WP2NOBEACON_ENABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75373P2.NoBeacon Enable bit. - 1: Controller drives P2.NoBeacon encoding for PHY power down state, when the link goes to L2. - 0: Controller drives P2 encoding for PHY power down state, when the link goes to L2.Note:This field is reserved (fixed to '0') if CX_P2NOBEACON_ENABLE is not set.Note: This register field is sticky.11110x1R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75381Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr754180x1C8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason.Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire.falsefalsefalsefalseLOOK_UP_IDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75404This number selects one entry to delete of the TRGT_CPL_LUT.3000x00000000R/WDELETE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75417This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field.This is a self-clearing register field. Reading from this register field always returns a '0'.31310x0WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFLINK_FLUSH_CONTROL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr754640x1CCR/W0xff000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFFLink Reset Request Flush Control Register.falsefalsefalsefalseAUTO_FLUSH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75446Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge.The flushing process is initiated if any of the following events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset.If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the Databook.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75454Reserved for future use.2310x000000RRSVD_I_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75463This is an internally reserved field. Do not use.Note: This register field is sticky.31240xffR/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFAMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr75594AXI Bridge Slave Error Response Register.0x1D0R/W0x00009c00PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFFAXI Bridge Slave Error Response Register.falsefalsefalsefalseAMBA_ERROR_RESPONSE_GLOBALPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75493Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data for non-posted requests) and ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and look at bit [2] for other scenarios.AXI: - 0: OKAY (with FFFF data for non-posted requests) - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)The error response mapping is not applicable to Non-existent Vendor ID register reads.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75501Reserved for future use.110x0RAMBA_ERROR_RESPONSE_VENDORIDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75520Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data). The controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERRORAXI: - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.220x0R/WAMBA_ERROR_RESPONSE_CRSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75542CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - always returns OKAYAXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75550Reserved for future use.950x00RAMBA_ERROR_RESPONSE_MAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75585AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request) -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) -> DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR -- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERRThe AXI bridge internally drops (processes internally but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave interface.The controller sets the AXI slave read databus to 0xFFFF for all error responses.Note: This register field is sticky.15100x27R/WRSVDP_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75593Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFAMBA_LINK_TIMEOUT_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr756410x1D4R/W0x00000032PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFFLink Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a "flush" timer. The timeout value of the timer is set by this register. If the timer times out before the PCIe link is operational, the bridge TX request queues are flushed. For more details, see the "AXI Bridge Initialization, Clocking and Reset" section in the AXI chapter of the Databook.falsefalsefalsefalseLINK_TIMEOUT_PERIOD_DEFAULTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75622Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests.The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is 4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between 16% and 17%.Note: This register field is sticky.700x32R/WLINK_TIMEOUT_ENABLE_DEFAULTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75632Disable Flush. You can disable the flush feature by setting this field to "1".Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75640Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFAMBA_ORDERING_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr757510x1D8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFFAMBA Ordering Control.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75652Reserved for future use.000x0RAX_SNP_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75666AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted Requests" section in the AXI chapter of the Databook.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75674Reserved for future use.220x0RAX_MSTR_ORDR_P_EVENT_SELPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75718AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, "NP must not pass P" at the AXI Master Interface.The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination. It does this by waiting for the all of the write responses on the B channel. This can affect the performance of the master read channel.For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave. - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. - 11: ReservedNote 2: This setting will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP write transactions which are always serialized with P write transactions.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75726Reserved for future use.650x0RAX_MSTR_ZEROLREAD_FWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75742AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is forward to the application.770x0R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75750Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFCOHERENCY_CONTROL_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr757880x1E0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFFACE Cache Coherency Control Register 1falsefalsefalsefalseCFG_MEMTYPE_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75765Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = PeripheralNote: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75773Reserved for future use.110x0RCFG_MEMTYPE_BOUNDARY_LOW_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75787Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are in the lower address space region; addresses equal or greater than this value are in the upper address space region.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFCOHERENCY_CONTROL_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr758030x1E4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFFACE Cache Coherency Control Register 2falsefalsefalsefalseCFG_MEMTYPE_BOUNDARY_HIGH_ADDRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75802Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFCOHERENCY_CONTROL_3_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr758610x1E8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFFACE Cache Coherency Control Register 3falsefalsefalsefalse--200x0rCFG_MSTR_ARCACHE_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75819Master Read CACHE Signal Behavior.Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE fieldNote: This register field is sticky.630x0R/W--1070x0rCFG_MSTR_AWCACHE_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75835Master Write CACHE Signal Behavior.Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE fieldNote: for message requests the value of mstr_awcache is always "0000" regardless of the value of this bitNote: This register field is sticky.14110x0R/W--18150x0rCFG_MSTR_ARCACHE_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75846Master Read CACHE Signal Value.Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'.Note: This register field is sticky.22190x0R/W--26230x0rCFG_MSTR_AWCACHE_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75860Master Write CACHE Signal Value.Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'.Note: not applicable to message requests; for message requests the value of mstr_awcache is always "0000"Note: This register field is sticky.30270x0R/W--31310x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFAXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr758940x1F0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFFLower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_LOW_RESERVEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75883Reserved for future use.Note: This register field is sticky.1100x000RCFG_AXIMSTR_MSG_ADDR_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75893Lower 20 bits of the programmable AXI address for Messages.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFAXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr759090x1F4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFFUpper 32 bits of the programmable AXI address where Messages coming from wire are mapped to.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75908Upper 32 bits of the programmable AXI address for Messages.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPCIE_VERSION_NUMBER_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr759340x1F8R0x3533302aPE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFFPCIe Controller IIP Release Version Number. The version number is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_NUMBERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75933Version Number.3100x3533302aRregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPCIE_VERSION_TYPE_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr759590x1FCR0x6c703038PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFFPCIe Controller IIP Release Version Type. The type is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75958Version Type.3100x6c703038RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFMSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr760010x240R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFFMSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75981MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present.Note: This register field is sticky.000x0R/WMSIX_ADDRESS_MATCH_RESERVED_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr75991Reserved.Note: This register field is sticky.110x0RMSIX_ADDRESS_MATCH_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76000MSI-X Address Match Low Address.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFMSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr760230x244R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFFMSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76022MSI-X Address Match High Address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFMSIX_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr760970x248W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_DOORBELL_OFFMSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. - For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF, the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.falsefalsefalsefalseMSIX_DOORBELL_VECTORPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76048MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.1000x000WMSIX_DOORBELL_RESERVED_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76055Reserved.11110x0WMSIX_DOORBELL_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76064MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with.14120x0WMSIX_DOORBELL_VF_ACTIVEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76073MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction.15150x0WMSIX_DOORBELL_VFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76081MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.23160x00WMSIX_DOORBELL_PFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76089MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction.28240x00WMSIX_DOORBELL_RESERVED_29_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76096Reserved.31290x0WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFMSIX_RAM_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr762350x24CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFFMSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook.falsefalsefalsefalseMSIX_RAM_CTRL_TABLE_DSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76115MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode.Note: This register field is sticky.000x0R/WMSIX_RAM_CTRL_TABLE_SDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76126MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode.Note: This register field is sticky.110x0R/WMSIX_RAM_CTRL_RESERVED_2_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76136Reserved.Note: This register field is sticky.720x00RMSIX_RAM_CTRL_PBA_DSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76147MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode.Note: This register field is sticky.880x0R/WMSIX_RAM_CTRL_PBA_SDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76158MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode.Note: This register field is sticky.990x0R/WMSIX_RAM_CTRL_RESERVED_10_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76168Reserved.Note: This register field is sticky.15100x00RMSIX_RAM_CTRL_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76184MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power signals for both RAMs.It is up to the application to ensure the RAMs are in the proper power state before trying to access them. Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality.Note: This register field is sticky.16160x0R/WMSIX_RAM_CTRL_RESERVED_17_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76194Reserved.Note: This register field is sticky.23170x00RMSIX_RAM_CTRL_DBG_TABLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76209MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.24240x0R/WMSIX_RAM_CTRL_DBG_PBAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76224MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.25250x0R/WMSIX_RAM_CTRL_RESERVED_26_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76234Reserved.Note: This register field is sticky.31260x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPL_LTR_LATENCY_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr763290x430R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFFLTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.falsefalsefalsefalseSNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76257Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 900x000R/WSNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76268Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 12100x0R/WRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76276Reserved for future use.14130x0RSNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76287Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 15150x0R/WNO_SNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76298No Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25160x000R/WNO_SNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76309No Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28260x0R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76317Reserved for future use.30290x0RNO_SNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76328No Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFAUX_CLK_FREQ_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr763640x440R/W0x00000018PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFFAuxiliary Clock Frequency Control Register.falsefalsefalsefalseAUX_CLK_FREQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76355The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted.If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).Note: This register field is sticky.900x018R/WRSVDP_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76363Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFL1_SUBSTATES_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr764240x444R/W0x000000d2PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_L1_SUBSTATES_OFFL1 Substates Timing Register.falsefalsefalsefalseL1SUB_T_POWER_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76377Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3.Note: This register field is sticky.100x2R/WL1SUB_T_L1_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76387Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15.Note: This register field is sticky.520x4R/WL1SUB_T_PCLKACKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76400Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be L1SUB_T_PCLKACK + 1. Range is 0..3Note: This register field is sticky.760x3R/WL1SUB_LOW_POWER_CLOCK_SWITCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76415If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the controller will delay the switching of aux_clk to the slow platform clock until it detects that the link partner has de-asserted CLKREQ#.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76423Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPOWERDOWN_CTRL_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr764850x448R/W0x00000220PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFFPowerdown Control and Status Register.falsefalsefalsefalsePOWERDOWN_FORCEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76443This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event that the P2 Powerdown transition does not complete. It will allow the controller to proceed with the transition to the P1 Powerdown state. This field always reads back as 1'b0.000x0WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76451Reserved for future use.310x0RPOWERDOWN_MAC_POWERDOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76462This field represents the Powerdown value driven by the controller to the PHY.740x2RPOWERDOWN_PHY_POWERDOWNPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76476This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller, when the PHY has returned the Phystatus acknowledgment for the Powerdown transition.1180x2RRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76484Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFGEN4_LANE_MARGINING_1_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr765730x480R/W0x05201409PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFFGen4 Lane Margining 1 Register.falsefalsefalsefalseMARGINING_NUM_TIMING_STEPSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76501M(NumTimingSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.500x09R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76509Reserved for future use.760x0RMARGINING_MAX_TIMING_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76522M(MaxTimingOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.1380x14R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76530Reserved for future use.15140x0RMARGINING_NUM_VOLTAGE_STEPSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76543M(NumVoltageSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.22160x20R/WRSVDP_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76551Reserved for future use.23230x0RMARGINING_MAX_VOLTAGE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76564M(MaxVoltageOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.29240x05R/WRSVDP_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76572Reserved for future use.31300x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFGEN4_LANE_MARGINING_2_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr767200x484R/W0x060f0000PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFFGen4 Lane Margining 2 Register.falsefalsefalsefalseMARGINING_SAMPLE_RATE_VOLTAGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76592M(SamplingRateVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateVoltage) is fixed to 63 internally.Note: This register field is sticky.500x00R/WRSVDP_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76600Reserved for future use.760x0RMARGINING_SAMPLE_RATE_TIMINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76616M(SamplingRateTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter , see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateTiming) is fixed to 63 internally.Note: This register field is sticky.1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76624Reserved for future use.15140x0RMARGINING_MAXLANESPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76637M(MaxLanes) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.20160x0fR/WRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76645Reserved for future use.23210x0RMARGINING_VOLTAGE_SUPPORTEDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76658M(VoltageSupported) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.24240x0R/WMARGINING_IND_UP_DOWN_VOLTAGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76671M(IndUpDownVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.25250x1R/WMARGINING_IND_LEFT_RIGHT_TIMINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76684M(IndLeftRightTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.26260x1R/WMARGINING_SAMPLE_REPORTING_METHODPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76698M(SampleReportingMethod) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.27270x0R/WMARGINING_IND_ERROR_SAMPLERPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76711M(IndErrorSampler) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76719Reserved for future use.30290x0R--31310x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPIPE_RELATED_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr767820x490R/W0x00000022PE0_DWC_pcie_ctl_DBI_Slave_PF0_PORT_LOGIC_PIPE_RELATED_OFFPIPE Related Register.This register controls the pipe's capabitity, control, and status parameters.falsefalsefalsefalseRX_MESSAGE_BUS_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76740RXMessageBusWriteBufferDepth defined in the PIPE Specification.Indicates the number of write buffer entries that the PHY has implemented to receive writes from the controller.If the value is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the controller issues only write_commited commands, never write_uncommitted.Note: This register field is sticky.300x2R/WTX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76754TXMessageBusMinWriteBufferDepth defined in the PIPE Specification.Indicates the minimum number of write buffer entries that the PHY expects the controller to implement to receive writes from it.Note: This register field is sticky.740x2RPIPE_GARBAGE_DATA_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76773PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set until when any of the following three conditions are true: -- RxValid is deasserted -- a valid RxStartBlock is received at 128b/130b encoding -- a valid COM symbol is received at 8b/10b encodingNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76781Reserved for future use.3190x000000RmemoryPE0_DWC_pcie_ctl.DBI_Slave.PF0_PCIE_CAP_DBI2PF0_PCIE_CAP_DBI2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_PCIE_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr767890x1000700xFR/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_PCIE_CAP_DBI2DBI2 Shadow Block: PF PCI Express Capability StructuregroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2PF0_MSIX_CAP_DBI2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr769210x1000B0RPE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2DBI2 Shadow Block: PF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGSHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr768340x0R0x00800000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76808Reserved for future use.1500x0000RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76824MSI-X Table Size in the shadow register.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76833Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_TABLE_OFFSET_REGSHADOW_MSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr768770x4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76858MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76876MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_MSIX_CAP_DBI2.SHADOW_MSIX_PBA_OFFSET_REGSHADOW_MSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr769200x8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76901MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.200x0RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_MSIX_CAP_DBI2_SHADOW_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76919MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 && MSIX_CAP_ENABLE=1 ) then R/W else RNote: This register field is sticky.3130x00000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2PF0_TPH_CAP_DBI2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr770770x100208RPE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_DBI2DBI2 Shadow Block: PF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_TPH_CAP_DBI2.SHADOW_TPH_REQ_CAP_REG_REGSHADOW_TPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr770760x4R0x00000001PE0_DWC_pcie_ctl_DBI_Slave_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REGShadow register TPH Requestor Capability Register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76941No ST Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76959Interrupt Vector Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76977Device Specific Mode Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr76986Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77004Extended TPH Requester Supported in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77022ST Table Location Bit 0 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77040ST Table Location Bit 1 in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77049Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77066ST Table Size in the shadow register.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else RNote: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_TPH_CAP_DBI2_SHADOW_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77075Reserved for future use.31270x00RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAPPF0_ATU_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1028740x300000R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAPATU Por Logic StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr771840x0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77095When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77106When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77115This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77126When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77138When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77150Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77163When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77183Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr773920x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77205MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77217TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77237TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77249TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77262Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77274Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77297TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77314Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77335Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77349DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77369CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77381Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77391Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr774290x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77417Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77428Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr774450xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77444Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr774720x10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77461Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77471Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr775010x14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77500When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr775150x18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77514Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr775470x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77534Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77546Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr776600x100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77561When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77574When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77587When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77600When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77613When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77625Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77639When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77659Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr779550x104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77685MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77710BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77728Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77739TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77750TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77762ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77775TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77789Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77808Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77821PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77837Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77853Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77872Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77887CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77899Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77944Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77954Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr779920x108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77980Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr77991Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr780060x10CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78005Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr780330x110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78022Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78032Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr780720x114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78058Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78071Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr780880x118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78087Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr781200x120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78107Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78119Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr782230x200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78134When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78145When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78154This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78165When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78177When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78189Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78202When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78222Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr784310x204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78244MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78256TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78276TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78288TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78301Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78313Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78336TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78353Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78374Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78388DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78408CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78420Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78430Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr784680x208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78456Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78467Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr784840x20CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78483Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr785110x210R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78500Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78510Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr785400x214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78539When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr785540x218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78553Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr785860x220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78573Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78585Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr786990x300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78600When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78613When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78626When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78639When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78652When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78664Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78678When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78698Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr789940x304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78724MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78749BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78767Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78778TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78789TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78801ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78814TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78828Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78847Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78860PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78876Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78892Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78911Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78926CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78938Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78983Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr78993Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr790310x308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79019Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79030Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr790450x30CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79044Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr790720x310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79061Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79071Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr791110x314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79097Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79110Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr791270x318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79126Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr791590x320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79146Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79158Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr792620x400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79173When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79184When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79193This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79204When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79216When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79228Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79241When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79261Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr794700x404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79283MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79295TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79315TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79327TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79340Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79352Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79375TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79392Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79413Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79427DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79447CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79459Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79469Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr795070x408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79495Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79506Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr795230x40CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79522Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr795500x410R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79539Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79549Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr795790x414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79578When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr795930x418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79592Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr796250x420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79612Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79624Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr797380x500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79639When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79652When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79665When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79678When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79691When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79703Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79717When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79737Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr800330x504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79763MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79788BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79806Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79817TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79828TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79840ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79853TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79867Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79886Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79899PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79915Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79931Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79950Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79965CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr79977Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80022Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80032Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr800700x508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80058Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80069Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr800840x50CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80083Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr801110x510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80100Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80110Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr801500x514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80136Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80149Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr801660x518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80165Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr801980x520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80185Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80197Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr803010x600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80212When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80223When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80232This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80243When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80255When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80267Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80280When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80300Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr805090x604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80322MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80334TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80354TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80366TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80379Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80391Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80414TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80431Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80452Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80466DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80486CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80498Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80508Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr805460x608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80534Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80545Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr805620x60CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80561Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr805890x610R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80578Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80588Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr806180x614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80617When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr806320x618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80631Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr806640x620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80651Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80663Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr807770x700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80678When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80691When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80704When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80717When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80730When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80742Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80756When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80776Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr810720x704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80802MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80827BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80845Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80856TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80867TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80879ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80892TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80906Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80925Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80938PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80954Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80970Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr80989Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81004CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81016Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81061Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81071Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr811090x708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81097Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81108Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr811230x70CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81122Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr811500x710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81139Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81149Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr811890x714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81175Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81188Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr812050x718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81204Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr812370x720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81224Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81236Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr813400x800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81251When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81262When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81271This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81282When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81294When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81306Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81319When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81339Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr815480x804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81361MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81373TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81393TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81405TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81418Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81430Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81453TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81470Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81491Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81505DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81525CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81537Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81547Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr815850x808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81573Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81584Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr816010x80CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81600Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr816280x810R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81617Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81627Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr816570x814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81656When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr816710x818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81670Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr817030x820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81690Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81702Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr818160x900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81717When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81730When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81743When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81756When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81769When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81781Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81795When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81815Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr821110x904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81841MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81866BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81884Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81895TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81906TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81918ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81931TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81945Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81964Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81977PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr81993Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82009Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82028Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82043CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82055Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82100Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82110Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr821480x908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82136Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82147Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr821620x90CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82161Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr821890x910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82178Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82188Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr822280x914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82214Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82227Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr822440x918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82243Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr822760x920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82263Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82275Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr823790xA00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82290When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82301When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82310This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82321When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82333When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82345Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82358When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82378Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr825870xA04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82400MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82412TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82432TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82444TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82457Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82469Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82492TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82509Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82530Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82544DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82564CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82576Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82586Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr826240xA08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82612Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82623Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr826400xA0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82639Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr826670xA10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82656Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82666Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr826960xA14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82695When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr827100xA18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82709Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr827420xA20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82729Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82741Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr828550xB00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82756When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82769When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82782When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82795When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82808When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82820Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82834When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82854Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr831500xB04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82880MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82905BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82923Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82934TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82945TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82957ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82970TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr82984Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83003Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83016PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83032Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83048Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83067Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83082CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83094Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83139Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83149Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr831870xB08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83175Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83186Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr832010xB0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83200Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr832280xB10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83217Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83227Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr832670xB14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83253Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83266Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr832830xB18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83282Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr833150xB20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83302Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83314Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr834180xC00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83329When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83340When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83349This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83360When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83372When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83384Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83397When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83417Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr836260xC04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83439MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83451TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83471TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83483TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83496Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83508Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83531TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83548Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83569Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83583DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83603CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83615Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83625Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr836630xC08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83651Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83662Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr836790xC0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83678Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr837060xC10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83695Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83705Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr837350xC14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83734When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr837490xC18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83748Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr837810xC20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83768Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83780Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr838940xD00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83795When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83808When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83821When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83834When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83847When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83859Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83873When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83893Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr841890xD04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83919MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83944BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83962Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83973TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83984TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr83996ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84009TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84023Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84042Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84055PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84071Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84087Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84106Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84121CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84133Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84178Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84188Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr842260xD08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84214Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84225Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr842400xD0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84239Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr842670xD10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84256Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84266Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr843060xD14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84292Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84305Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr843220xD18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84321Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr843540xD20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84341Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84353Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr844570xE00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84368When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84379When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84388This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84399When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84411When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84423Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84436When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84456Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr846650xE04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84478MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84490TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84510TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84522TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84535Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84547Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84570TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84587Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84608Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84622DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84642CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84654Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84664Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr847020xE08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84690Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84701Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr847180xE0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84717Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr847450xE10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84734Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84744Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr847740xE14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84773When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr847880xE18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84787Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr848200xE20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84807Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84819Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr849330xF00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84834When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84847When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84860When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84873When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84886When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84898Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84912When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84932Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr852280xF04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84958MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr84983BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85001Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85012TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85023TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85035ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85048TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85062Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85081Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85094PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85110Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85126Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85145Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85160CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85172Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85217Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85227Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr852650xF08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85253Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85264Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr852790xF0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85278Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr853060xF10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85295Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85305Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr853450xF14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85331Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85344Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr853610xF18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85360Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr853930xF20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85380Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85392Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr854960x1000R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85407When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85418When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85427This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85438When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85450When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85462Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85475When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85495Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr857040x1004R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85517MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85529TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85549TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85561TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85574Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85586Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85609TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85626Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85647Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85661DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85681CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85693Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85703Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr857410x1008R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85729Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85740Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr857570x100CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85756Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr857840x1010R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85773Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85783Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr858130x1014R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85812When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr858270x1018R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85826Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr858590x1020R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85846Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85858Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr859720x1100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85873When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85886When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85899When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85912When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85925When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85937Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85951When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85971Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr862670x1104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr85997MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86022BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86040Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86051TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86062TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86074ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86087TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86101Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86120Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86133PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86149Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86165Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86184Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86199CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86211Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86256Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86266Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr863040x1108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86292Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86303Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr863180x110CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86317Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr863450x1110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86334Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86344Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr863840x1114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86370Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86383Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr864000x1118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86399Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr864320x1120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86419Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86431Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr865350x1200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86446When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86457When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86466This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86477When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86489When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86501Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86514When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86534Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr867430x1204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86556MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86568TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86588TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86600TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86613Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86625Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86648TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86665Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86686Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86700DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86720CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86732Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86742Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr867800x1208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86768Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86779Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr867960x120CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86795Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr868230x1210R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86812Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86822Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr868520x1214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86851When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr868660x1218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86865Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr868980x1220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86885Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86897Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr870110x1300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86912When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86925When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86938When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86951When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86964When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86976Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr86990When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87010Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr873060x1304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87036MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87061BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87079Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87090TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87101TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87113ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87126TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87140Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87159Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87172PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87188Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87204Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87223Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87238CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87250Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87295Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87305Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr873430x1308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87331Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87342Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr873570x130CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87356Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr873840x1310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87373Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87383Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr874230x1314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87409Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87422Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr874390x1318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87438Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr874710x1320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87458Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87470Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr875740x1400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87485When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87496When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87505This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87516When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87528When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87540Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87553When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87573Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr877820x1404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87595MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87607TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87627TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87639TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87652Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87664Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87687TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87704Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87725Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87739DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87759CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87771Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87781Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr878190x1408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87807Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87818Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr878350x140CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87834Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr878620x1410R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87851Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87861Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr878910x1414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87890When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr879050x1418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87904Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr879370x1420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87924Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87936Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr880500x1500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87951When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87964When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87977When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr87990When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88003When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88015Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88029When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88049Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr883450x1504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88075MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88100BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88118Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88129TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88140TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88152ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88165TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88179Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88198Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88211PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88227Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88243Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88262Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88277CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88289Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88334Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88344Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr883820x1508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88370Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88381Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr883960x150CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88395Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr884230x1510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88412Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88422Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr884620x1514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88448Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88461Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr884780x1518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88477Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr885100x1520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88497Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88509Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr886130x1600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88524When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88535When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88544This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88555When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88567When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88579Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88592When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88612Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr888210x1604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88634MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88646TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88666TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88678TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88691Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88703Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88726TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88743Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88764Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88778DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88798CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88810Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88820Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr888580x1608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88846Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88857Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr888740x160CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88873Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr889010x1610R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88890Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88900Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr889300x1614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88929When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr889440x1618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88943Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr889760x1620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88963Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88975Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr890890x1700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr88990When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89003When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89016When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89029When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89042When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89054Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89068When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89088Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr893840x1704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89114MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89139BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89157Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89168TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89179TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89191ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89204TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89218Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89237Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89250PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89266Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89282Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89301Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89316CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89328Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89373Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89383Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr894210x1708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89409Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89420Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr894350x170CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89434Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr894620x1710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89451Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89461Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr895010x1714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89487Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89500Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr895170x1718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89516Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr895490x1720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89536Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89548Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr896520x1800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89563When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89574When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89583This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89594When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89606When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89618Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89631When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89651Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr898600x1804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89673MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89685TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89705TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89717TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89730Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89742Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89765TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89782Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89803Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89817DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89837CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89849Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89859Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr898970x1808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89885Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89896Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr899130x180CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89912Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr899400x1810R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89929Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89939Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr899690x1814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89968When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr899830x1818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr89982Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr900150x1820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90002Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90014Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr901280x1900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90029When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90042When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90055When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90068When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90081When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90093Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90107When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90127Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr904230x1904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90153MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90178BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90196Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90207TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90218TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90230ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90243TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90257Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90276Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90289PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90305Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90321Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90340Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90355CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90367Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90412Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90422Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr904600x1908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90448Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90459Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr904740x190CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90473Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr905010x1910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90490Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90500Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr905400x1914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90526Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90539Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr905560x1918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90555Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr905880x1920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90575Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90587Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr906910x1A00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90602When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90613When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90622This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90633When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90645When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90657Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90670When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90690Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr908990x1A04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90712MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90724TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90744TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90756TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90769Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90781Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90804TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90821Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90842Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90856DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90876CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90888Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90898Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr909360x1A08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90924Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90935Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr909520x1A0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90951Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr909790x1A10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90968Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr90978Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr910080x1A14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91007When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr910220x1A18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91021Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr910540x1A20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91041Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91053Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr911670x1B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91068When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91081When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91094When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91107When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91120When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91132Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91146When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91166Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr914620x1B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91192MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91217BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91235Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91246TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91257TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91269ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91282TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91296Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91315Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91328PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91344Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91360Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91379Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91394CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91406Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91451Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91461Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr914990x1B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91487Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91498Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr915130x1B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91512Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr915400x1B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91529Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91539Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr915790x1B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91565Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91578Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr915950x1B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91594Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr916270x1B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91614Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91626Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr917300x1C00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91641When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91652When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91661This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91672When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91684When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91696Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91709When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91729Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr919380x1C04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91751MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91763TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91783TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91795TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91808Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91820Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91843TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91860Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91881Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91895DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91915CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91927Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91937Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr919750x1C08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91963Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91974Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr919910x1C0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr91990Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr920180x1C10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92007Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92017Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr920470x1C14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92046When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr920610x1C18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92060Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr920930x1C20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92080Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92092Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr922060x1D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92107When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92120When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92133When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92146When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92159When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92171Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92185When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92205Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr925010x1D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92231MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92256BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92274Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92285TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92296TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92308ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92321TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92335Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92354Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92367PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92383Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92399Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92418Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92433CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92445Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92490Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92500Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr925380x1D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92526Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92537Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr925520x1D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92551Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr925790x1D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92568Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92578Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr926180x1D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92604Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92617Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr926340x1D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92633Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr926660x1D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92653Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92665Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr927690x1E00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92680When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92691When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92700This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92711When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92723When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92735Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92748When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92768Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr929770x1E04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92790MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92802TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92822TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92834TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92847Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92859Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92882TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92899Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92920Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92934DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92954CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92966Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr92976Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr930140x1E08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93002Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93013Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr930300x1E0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93029Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr930570x1E10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93046Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93056Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr930860x1E14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93085When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr931000x1E18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93099Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr931320x1E20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93119Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93131Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr932450x1F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93146When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93159When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93172When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93185When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93198When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93210Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93224When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93244Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr935400x1F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93270MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93295BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93313Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93324TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93335TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93347ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93360TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93374Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93393Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93406PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93422Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93438Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93457Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93472CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93484Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93529Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93539Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr935770x1F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93565Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93576Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr935910x1F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93590Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr936180x1F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93607Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93617Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr936570x1F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93643Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93656Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr936730x1F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93672Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr937050x1F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93692Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93704Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr938180x2100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93719When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93732When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93745When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93758When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93771When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93783Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93797When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93817Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr941130x2104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93843MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93868BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93886Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93897TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93908TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93920ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93933TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93947Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93966Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93979PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr93995Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94011Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94030Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94045CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94057Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94102Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94112Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr941500x2108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94138Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94149Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr941640x210CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94163Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr941910x2110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94180Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94190Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr942300x2114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94216Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94229Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr942460x2118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94245Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr942780x2120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94265Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94277Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr943910x2300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94292When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94305When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94318When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94331When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94344When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94356Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94370When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94390Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr946860x2304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94416MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94441BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94459Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94470TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94481TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94493ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94506TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94520Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94539Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94552PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94568Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94584Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94603Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94618CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94630Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94675Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94685Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr947230x2308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94711Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94722Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr947370x230CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94736Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr947640x2310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94753Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94763Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr948030x2314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94789Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94802Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr948190x2318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94818Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr948510x2320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94838Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94850Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr949640x2500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94865When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94878When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94891When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94904When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94917When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94929Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94943When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94963Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr952590x2504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr94989MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95014BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95032Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95043TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95054TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95066ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95079TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95093Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95112Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95125PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95141Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95157Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95176Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95191CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95203Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95248Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95258Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr952960x2508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95284Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95295Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr953100x250CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95309Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr953370x2510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95326Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95336Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr953760x2514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95362Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95375Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr953920x2518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95391Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr954240x2520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95411Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95423Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr955370x2700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95438When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95451When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95464When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95477When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95490When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95502Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95516When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95536Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr958320x2704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95562MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95587BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95605Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95616TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95627TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95639ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95652TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95666Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95685Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95698PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95714Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95730Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95749Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95764CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95776Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95821Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95831Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr958690x2708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95857Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95868Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr958830x270CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95882Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr959100x2710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95899Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95909Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr959490x2714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95935Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95948Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr959650x2718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95964Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr959970x2720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95984Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr95996Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr961100x2900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96011When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96024When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96037When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96050When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96063When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96075Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96089When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96109Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr964050x2904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96135MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96160BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96178Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96189TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96200TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96212ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96225TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96239Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96258Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96271PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96287Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96303Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96322Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96337CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96349Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96394Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96404Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr964420x2908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96430Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96441Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr964560x290CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96455Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr964830x2910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96472Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96482Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr965220x2914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96508Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96521Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr965380x2918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96537Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr965700x2920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96557Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96569Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr966830x2B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96584When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96597When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96610When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96623When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96636When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96648Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96662When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96682Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr969780x2B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96708MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96733BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96751Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96762TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96773TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96785ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96798TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96812Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96831Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96844PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96860Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96876Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96895Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96910CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96922Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96967Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr96977Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr970150x2B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97003Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97014Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr970290x2B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97028Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr970560x2B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97045Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97055Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr970950x2B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97081Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97094Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr971110x2B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97110Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr971430x2B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97130Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97142Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr972560x2D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97157When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97170When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97183When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97196When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97209When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97221Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97235When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97255Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr975510x2D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97281MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97306BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97324Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97335TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97346TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97358ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97371TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97385Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97404Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97417PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97433Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97449Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97468Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97483CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97495Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97540Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97550Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr975880x2D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97576Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97587Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr976020x2D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97601Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr976290x2D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97618Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97628Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr976680x2D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97654Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97667Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr976840x2D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97683Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr977160x2D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97703Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97715Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr978290x2F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97730When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97743When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97756When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97769When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97782When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97794Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97808When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97828Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr981240x2F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97854MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97879BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97897Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97908TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97919TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97931ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97944TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97958Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97977Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr97990PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98006Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98022Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98041Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98056CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98068Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98113Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98123Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr981610x2F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98149Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98160Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr981750x2F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98174Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr982020x2F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98191Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98201Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr982410x2F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98227Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98240Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr982570x2F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98256Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr982890x2F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98276Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98288Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr984020x3100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98303When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98316When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98329When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98342When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98355When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98367Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98381When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98401Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr986970x3104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98427MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98452BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98470Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98481TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98492TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98504ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98517TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98531Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98550Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98563PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98579Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98595Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98614Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98629CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98641Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98686Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98696Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr987340x3108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98722Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98733Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr987480x310CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98747Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr987750x3110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98764Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98774Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr988140x3114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98800Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98813Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr988300x3118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98829Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr988620x3120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98849Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98861Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr989750x3300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98876When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98889When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98902When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98915When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98928When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98940Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98954When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr98974Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr992700x3304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99000MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99025BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99043Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99054TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99065TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99077ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99090TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99104Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99123Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99136PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99152Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99168Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99187Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99202CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99214Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99259Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99269Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr993070x3308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99295Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99306Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr993210x330CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99320Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr993480x3310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99337Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99347Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr993870x3314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99373Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99386Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr994030x3318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99402Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr994350x3320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99422Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99434Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr995480x3500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99449When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99462When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99475When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99488When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99501When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99513Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99527When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99547Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr998430x3504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99573MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99598BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99616Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99627TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99638TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99650ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99663TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99677Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99696Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99709PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99725Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99741Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99760Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99775CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99787Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99832Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99842Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr998800x3508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99868Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99879Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr998940x350CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99893Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr999210x3510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99910Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99920Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr999600x3514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99946Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99959Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr999760x3518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99975Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1000080x3520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr99995Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100007Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1001210x3700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100022When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100035When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100048When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100061When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100074When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100086Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100100When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100120Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1004160x3704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100146MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100171BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100189Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100200TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100211TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100223ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100236TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100250Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100269Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100282PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100298Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100314Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100333Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100348CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100360Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100405Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100415Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1004530x3708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100441Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100452Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1004670x370CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100466Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1004940x3710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100483Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100493Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1005330x3714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100519Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100532Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1005490x3718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100548Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1005810x3720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100568Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100580Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1006940x3900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100595When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100608When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100621When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100634When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100647When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100659Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100673When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100693Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1009890x3904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100719MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100744BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100762Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100773TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100784TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100796ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100809TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100823Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100842Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100855PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100871Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100887Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100906Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100921CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100933Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100978Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr100988Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1010260x3908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101014Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101025Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1010400x390CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101039Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1010670x3910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101056Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101066Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1011060x3914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101092Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101105Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1011220x3918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101121Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1011540x3920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101141Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101153Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1012670x3B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101168When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101181When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101194When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101207When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101220When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101232Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101246When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101266Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1015620x3B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101292MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101317BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101335Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101346TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101357TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101369ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101382TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101396Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101415Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101428PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101444Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101460Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101479Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101494CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101506Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101551Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101561Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1015990x3B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101587Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101598Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1016130x3B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101612Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1016400x3B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101629Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101639Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1016790x3B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101665Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101678Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1016950x3B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101694Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1017270x3B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101714Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101726Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1018400x3D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101741When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101754When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101767When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101780When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101793When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101805Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101819When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101839Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1021350x3D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101865MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101890BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101908Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101919TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101930TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101942ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101955TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101969Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr101988Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102001PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102017Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102033Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102052Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102067CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102079Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102124Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102134Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1021720x3D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102160Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102171Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1021860x3D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102185Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1022130x3D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102202Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102212Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1022520x3D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102238Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102251Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1022680x3D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102267Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1023000x3D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102287Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102299Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1024130x3F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102314When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102327When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102340When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102353When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102366When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102378Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102392When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102412Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1027080x3F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102438MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102463BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102481Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102492TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102503TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102515ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102528TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102542Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102561Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102574PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102590Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102606Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102625Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102640CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102652Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102697Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102707Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1027450x3F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102733Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102744Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1027590x3F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102758Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1027860x3F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102775Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102785Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1028250x3F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102811Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102824Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1028410x3F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102840Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1028730x3F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102860Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102872Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAPPF0_DMA_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1092220x380000R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAPDMA Port Logic StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFDMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1029520x0R/W0x00000688PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFFDMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx Requests - DMA Write Channel MRd Requests (DMA data requests and LL element/descriptor access) - DMA Read Channel MRd Requests (LL element/descriptor access) - DMA Read Channel MWr RequestsConcurrent traffic from channels with same priority are sorted according to Round-Robin arbitration rules.The arbitration priority defaults to Non-DMA requests (highest), Write Channel MRd, Read Channel MRd, Read Channel MWr.For more details, see the For more details, see the Internal Architecture section in the DMA chapter of the Databook.falsefalsefalsefalseRTRGT1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102908Non-DMA Rx Requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0R/WWR_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102920DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 530x1R/WRD_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102932DMA Read Channel MRd Requests. For LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 860x2R/WRDBUFF_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102943DMA Read Channel MWr Requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1190x3R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102951Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFDMA_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1030280x8R/W0x00040004PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CTRL_OFFDMA Number of Channels Register.falsefalsefalsefalseNUM_DMA_WR_CHANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102965Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support.300x4RRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102973Reserved for future use.1540x000RNUM_DMA_RD_CHANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102983Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support.19160x4RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr102991Reserved for future use.23200x0RDIS_C2W_CACHE_WRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103005Disable DMA Write Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDIS_C2W_CACHE_RDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103019Disable DMA Read Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103027Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFDMA_WRITE_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1031870xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFFDMA Write Engine Enable Register.falsefalsefalsefalseDMA_WRITE_ENGINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103082DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this bit to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the DMA controller write logic re-initializes the control logic, ensuring that the next DMA write transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" , after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped." Resetting the DMA controller write logic re-initializes the control logic ensuring that the next DMA write transfer is executed successfully. - During software development, when you incorrectly program the DMA write engine.To "Soft Reset" the DMA controller write logic, you must: - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert the DMA write engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103090Reserved for future use.1510x0000RDMA_WRITE_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103101Enable Handshake for DMA Write Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16160x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103112Enable Handshake for DMA Write Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 17170x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103123Enable Handshake for DMA Write Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 18180x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103134Enable Handshake for DMA Write Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19190x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103145Enable Handshake for DMA Write Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 20200x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103156Enable Handshake for DMA Write Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21210x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103167Enable Handshake for DMA Write Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103178Enable Handshake for DMA Write Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103186Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFDMA_WRITE_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1032400x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFFDMA Write Doorbell Register.falsefalsefalsefalseWR_DOORBELL_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103210Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to toggle or write any other value to this register to start a new transfer.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103218Reserved for future use.3030x0000000RWR_STOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103239Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)."Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1033220x18R/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103268Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WWRITE_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103283Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WWRITE_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103298Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WWRITE_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103313Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103321Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1034040x1CR/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103350Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WWRITE_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103365Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WWRITE_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103380Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WWRITE_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103395Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103403Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFDMA_READ_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1035620x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFFDMA Read Engine Enable Register.falsefalsefalsefalseDMA_READ_ENGINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103457DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this field to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the DMA controller read logic re-initializes the control logic, ensuring that the next DMA read transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit", after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped". Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA read transfer is executed successfully. - During software development, when you incorrectly program the DMA read engine.To "Soft Reset" the DMA controller read logic, you must: - De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA read engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA read transfer does not start until you write to the "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103465Reserved for future use.1510x0000RDMA_READ_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103476Enable Handshake for DMA Read Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16160x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103487Enable Handshake for DMA Read Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 17170x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103498Enable Handshake for DMA Read Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 18180x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103509Enable Handshake for DMA Read Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19190x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103520Enable Handshake for DMA Read Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 20200x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103531Enable Handshake for DMA Read Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21210x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103542Enable Handshake for DMA Read Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103553Enable Handshake for DMA Read Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103561Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFDMA_READ_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1036130x30R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DOORBELL_OFFDMA Read Doorbell Register.falsefalsefalsefalseRD_DOORBELL_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103583Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103591Reserved for future use.3030x0000000RRD_STOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103612Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1036900x38R/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103639Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WREAD_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103653Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WREAD_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103667Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WREAD_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103681Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103689Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1037670x3CR/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103716Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 400x01R/WREAD_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103730Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 950x01R/WREAD_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103744Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 14100x01R/WREAD_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103758Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103766Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFDMA_WRITE_INT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1038410x4CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFFDMA Write Interrupt Status Register.falsefalsefalsefalseWR_DONE_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103797Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103805Reserved for future use.1580x00RWR_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103832Abort Interrupt Status. The DMA write channel has detected an error, or you manually stopped the transfer as described in "Error Handling Assistance by Remote Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103840Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFDMA_WRITE_INT_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1038890x54R/W0x000f000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFFDMA Write Interrupt Mask Register.falsefalsefalsefalseWR_DONE_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103858Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103866Reserved for future use.1580x00RWR_ABORT_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103880Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103888Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFDMA_WRITE_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1039410x58R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFFDMA Write Interrupt Clear Register.falsefalsefalsefalseWR_DONE_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103908Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".300x0W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103916Reserved for future use.1580x00RWR_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103932Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".19160x0W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103940Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFDMA_WRITE_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1040030x5CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFFDMA Write Error Status RegisterfalsefalsefalsefalseAPP_READ_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103966Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103973Reserved for future use.1580x00RLINKLIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr103995Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104002Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFDMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1040200x60R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFFDMA Write Done IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_DONE_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104019The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFDMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1040360x64R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFFDMA Write Done IMWr Interrupt Address High Register.falsefalsefalsefalseDMA_WRITE_DONE_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104035The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFDMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1040540x68R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFFDMA Write Abort IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_ABORT_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104053The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1040700x6CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA Write Abort IMWr Address High Register.falsefalsefalsefalseDMA_WRITE_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104069The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFDMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1040980x70R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFFDMA Write Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104085The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104097The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFDMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1041260x74R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFFDMA Write Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104113The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104125The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFDMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1041540x78R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFFDMA Write Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104141The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104153The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFDMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1041820x7CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFFDMA Write Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104169The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WWR_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104181The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1042400x90R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseWR_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104206Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104214Reserved for future use.1580x00RWR_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104231Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104239Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFDMA_READ_INT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1043170xA0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFFDMA Read Interrupt Status Register.falsefalsefalsefalseRD_DONE_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104269Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104277Reserved for future use.1580x00RRD_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104308Abort Interrupt Status. The DMA read channel has detected an error, or you manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.You can read the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104316Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFDMA_READ_INT_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1043650xA8R/W0x000f000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_MASK_OFFDMA Read Interrupt Mask Register.falsefalsefalsefalseRD_DONE_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104334Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104342Reserved for future use.1580x00RRD_ABORT_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104356Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104364Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFDMA_READ_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1044170xACR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFFDMA Read Interrupt Clear Register.falsefalsefalsefalseRD_DONE_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104384Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".700x00WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104392Reserved for future use.1580x00RRD_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104408Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".23160x00WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104416Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFDMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1044850xB4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFFDMA Read Error Status Low Register.falsefalsefalsefalseAPP_WR_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104447Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer from the beginning, as the channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104454Reserved for future use.1580x00RLINK_LIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104477Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104484Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFDMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1045860xB8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFFDMA Read Error Status High Register.falsefalsefalsefalseUNSUPPORTED_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104512Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.700x00RCPL_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104536Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode".Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.1580x00RCPL_TIMEOUTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104559Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request, or a malformed CplD has been received. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.23160x00RDATA_POISIONINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104585Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request).The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFDMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1046430xC4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFFDMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseRD_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104609Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104617Reserved for future use.1580x00RRD_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104634Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104642Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFDMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1046600xCCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFFDMA Read Done IMWr Address Low Register.falsefalsefalsefalseDMA_READ_DONE_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104659The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFDMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1046760xD0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFFDMA Read Done IMWr Address High Register.falsefalsefalsefalseDMA_READ_DONE_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104675The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFDMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1046930xD4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFFDMA Read Abort IMWr Address Low Register.falsefalsefalsefalseDMA_READ_ABORT_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104692The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFDMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1047090xD8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFFDMA Read Abort IMWr Address High Register.falsefalsefalsefalseDMA_READ_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104708The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFDMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1047370xDCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFFDMA Read Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104724The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104736The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFDMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1047650xE0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFFDMA Read Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104752The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104764The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFDMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1047930xE4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFFDMA Read Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104780The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104792The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFDMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1048210xE8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFFDMA Read Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104808The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 1500x0000R/WRD_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104820The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1048940x108R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA Write Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104835DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104842Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104852DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104859Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104869DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104876Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104886DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104893Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1049670x10CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Write Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104908DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104915Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104925DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104932Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104942DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104949Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104959DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104966Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1050400x118R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA Read Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104981DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104988Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr104998DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105005Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105015DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105022Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105032DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105039Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1051130x11CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Read Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105054DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105061Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105071DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105078Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105088DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105095Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105105DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105112Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1054200x200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105133Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105152Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105169Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105190Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105211Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105232Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105244Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105262Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105275Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105287Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105303Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105315Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105337Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105351Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105365Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105379Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105391Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105405Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105419Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1054760x204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105436Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105448Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105461Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105475TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1055070x208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105506DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1055280x20CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105527Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1055460x210R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105545Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1055670x214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105566Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1055860x218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105585Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1056080x21CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105607Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1056270x220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105626Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1059340x300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105647Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105666Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105683Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105704Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105725Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105746Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105758Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105776Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105789Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105801Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105817Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105829Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105851Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105865Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105879Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105893Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105905Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105919Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105933Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1059900x304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105950Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105962Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105975Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr105989TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1060210x308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106020DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1060420x30CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106041Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1060600x310R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106059Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1060810x314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106080Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1060990x318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106098Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1061210x31CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106120Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1061400x320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106139Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1064470x400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106160Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106179Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106196Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106217Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106238Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106259Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106271Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106289Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106302Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106314Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106330Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106342Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106364Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106378Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106392Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106406Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106418Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106432Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106446Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1065030x404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106463Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106475Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106488Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106502TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1065340x408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106533DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1065550x40CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106554Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1065730x410R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106572Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1065940x414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106593Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1066130x418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106612Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1066350x41CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106634Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1066540x420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106653Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1069610x500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106674Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106693Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106710Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106731Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106752Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106773Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106785Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106803Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106816Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106828Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106844Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106856Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106878Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106892Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106906Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106920Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106932Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106946Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106960Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1070170x504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106977Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr106989Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107002Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107016TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1070480x508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107047DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1070690x50CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107068Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1070870x510R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107086Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1071080x514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107107Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1071260x518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107125Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1071480x51CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107147Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1071670x520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107166Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1074740x600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107187Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107206Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107223Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107244Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107265Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107286Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107298Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107316Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107329Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107341Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107357Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107369Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107391Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107405Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107419Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107433Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107445Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107459Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107473Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1075300x604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107490Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107502Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107515Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107529TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1075610x608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107560DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1075820x60CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107581Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1076000x610R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107599Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1076210x614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107620Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1076400x618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107639Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1076620x61CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107661Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1076810x620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107680Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1079880x700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107701Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107720Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107737Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107758Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107779Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107800Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107812Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107830Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107843Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107855Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107871Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107883Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107905Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107919Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107933Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107947Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107959Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107973Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr107987Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1080440x704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108004Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108016Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108029Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108043TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1080750x708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108074DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1080960x70CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108095Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1081140x710R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108113Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1081350x714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108134Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1081530x718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108152Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1081750x71CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108174Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1081940x720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108193Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1085010x800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108214Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108233Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108250Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108271Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108292Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108313Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108325Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108343Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108356Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108368Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108384Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108396Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108418Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108432Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108446Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108460Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108472Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108486Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108500Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1085570x804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108517Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108529Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108542Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108556TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1085880x808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108587DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1086090x80CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108608Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1086270x810R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108626Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1086480x814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108647Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1086670x818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108666Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1086890x81CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108688Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1087080x820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108707Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1090150x900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108728Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108747Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108764Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108785Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108806Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108827Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108839Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108857Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108870Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108882Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108898Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108910Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108932Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108946Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108960Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108974Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr108986Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109000Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109014Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1090710x904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109031Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109043Reserved.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109056Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109070TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1091020x908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109101DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1091230x90CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109122Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1091410x910R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109140Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1091620x914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109161Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1091800x918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109179Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1092020x91CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109201Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_dbi_cpcie_dsp_4x8.csr1092210x920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SETDWC_pcie_dbi_cpcie_dsp_4x8.csr109220Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W 3100x00000000R/W
Addressmap Information for 'DWC_pcie_dbi_cpcie_dsp_4x8'